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101. 发明授权

US07898285B2 Optimal local supply voltage determination circuit 失效
标题翻译：最佳本地电源电压确定电路
公开(公告)号：US07898285B2
公开(公告)日：2011-03-01
申请号：US12055569
申请日：2008-03-26
申请人： Kerry Bernstein , David S. Wolpert
发明人： Kerry Bernstein , David S. Wolpert
IPC分类号： H03K19/00
CPC分类号： G01R31/3004
摘要： A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each test circuit. Each test is performed with a critical test vector and a local supply voltage that decreases from test to test. The outputs of successive tests are compared in each test circuit. The tests are performed iteratively with successive reduction in the value of the local supply voltage until at least one stage of the logic circuits produces non-matching results between the first and second register. The voltage immediately before producing such non-matching results is the minimum operational voltage for the local voltage island.
摘要翻译：提供了一种测试电路，用于比较两种测试与不同本地电源电压之间的测试结果。逻辑电路的每个级的输出被存储在每个测试电路的第一寄存器中。每个测试都用临界测试矢量和从测试到测试的局部电源电压进行。在每个测试电路中比较连续测试的输出。迭代地执行测试，连续减小本地电源电压的值，直到至少一级的逻辑电路在第一和第二寄存器之间产生不匹配的结果。在产生这种不匹配结果之前的电压是本地电压岛的最小工作电压。

102. 发明申请

US20110027962A1 TRENCH DECOUPLING CAPACITOR FORMED BY RIE LAG OF THROUGH SILICON VIA (TSV) ETCH 失效
标题翻译：通过硅橡胶（TSV）蚀刻的RIE胶带形成的TRENCH解压电容器
公开(公告)号：US20110027962A1
公开(公告)日：2011-02-03
申请号：US12511545
申请日：2009-07-29
申请人： Kerry Bernstein , Francis R. White
发明人： Kerry Bernstein , Francis R. White
IPC分类号： H01L21/02
CPC分类号： H01L21/3065 , H01L21/76898 , H01L29/66181
摘要： A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag.
摘要翻译：使用通过硅通孔（TSV）蚀刻的RIE滞后来形成沟槽去耦电容器。一种方法包括在单个RIE工艺中蚀刻晶片中的通孔沟槽和电容器沟槽。通孔沟槽具有第一深度，并且由于RIE滞后，电容器沟槽具有小于第一深度的第二深度。

103. 发明授权

US07848128B2 Apparatus and method for implementing matrix-based search capability in content addressable memory devices 有权
标题翻译：在内容可寻址存储设备中实现基于矩阵的搜索能力的装置和方法
公开(公告)号：US07848128B2
公开(公告)日：2010-12-07
申请号：US11949063
申请日：2007-12-03
申请人： Igor Arsovski , Kerry Bernstein
发明人： Igor Arsovski , Kerry Bernstein
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.
摘要翻译：一种内容可寻址存储器（CAM）装置，包括排列成字线方向的存储单元阵列和排列在位线方向上的列，以及比较电路，被配置为将呈现给阵列的数据与存储在每行和列中的数据进行比较并且同时指示阵列的每一行和列上的匹配结果，从而导致二维的基于矩阵的数据比较操作。

104. 发明授权

US07700410B2 Chip-in-slot interconnect for 3D chip stacks 失效
标题翻译：用于3D芯片堆栈的片上插槽互连
公开(公告)号：US07700410B2
公开(公告)日：2010-04-20
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L21/44
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

105. 发明申请

US20100044759A1 DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS 有权
标题翻译：双面集成电路板
公开(公告)号：US20100044759A1
公开(公告)日：2010-02-25
申请号：US12612957
申请日：2009-11-05
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/786 , H01L21/18 , H01L21/768 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译：一种半导体结构及其制造方法。该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。下晶片可以包括布线水平。下部晶片可以包括用于触点的着陆焊盘。与下晶片的硅层的接触可以被硅化。

106. 发明申请

US20100006850A1 BEOL COMPATIBLE FET STRUCTURE 有权
标题翻译： BEOL兼容FET结构
公开(公告)号：US20100006850A1
公开(公告)日：2010-01-14
申请号：US12561827
申请日：2009-09-17
申请人： Christy S. Tyberg , Katherine L. Saenger , Jack O. Chu , Harold J. Hovel , Robert L. Wisnieff , Kerry Bernstein , Stephen W. Bedell
发明人： Christy S. Tyberg , Katherine L. Saenger , Jack O. Chu , Harold J. Hovel , Robert L. Wisnieff , Kerry Bernstein , Stephen W. Bedell
IPC分类号： H01L23/522 , H01L29/786 , H01L29/04
CPC分类号： H01L23/5226 , H01L23/53271 , H01L27/124 , H01L27/1248 , H01L2924/0002 , H01L2924/00
摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.
摘要翻译：本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

107. 发明申请

US20090308578A1 ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY 有权
公开(公告)号：US20090308578A1
公开(公告)日：2009-12-17
申请号：US12544344
申请日：2009-08-20
申请人： Kerry Bernstein , Thomas Brunschwiler , Bruno Michel
发明人： Kerry Bernstein , Thomas Brunschwiler , Bruno Michel
IPC分类号： F28D15/00
CPC分类号： H01L23/49827 , H01L23/46 , H01L23/473 , H01L25/0657 , H01L2224/16 , H01L2225/06541 , H01L2225/06589 , H01L2924/15159 , H01L2924/3011
摘要： An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

108. 发明申请

US20090224803A1 CMOS BACK-GATED KEEPER TECHNIQUE 失效
公开(公告)号：US20090224803A1
公开(公告)日：2009-09-10
申请号：US12045500
申请日：2008-03-10
申请人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
发明人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
IPC分类号： H03K19/20
CPC分类号： H03K19/0008 , H03K3/356104 , H03K2217/0018
摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

109. 发明授权

US07521950B2 Wafer level I/O test and repair enabled by I/O layer 失效
标题翻译：通过I / O层启用晶圆级I / O测试和修复
公开(公告)号：US07521950B2
公开(公告)日：2009-04-21
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , G01R31/00 , G01N37/00 , G06F13/20 , G06F13/36 , G06F11/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

110. 发明申请

US20080291767A1 MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL 审中-公开
标题翻译：多个水平多端口注册文件
公开(公告)号：US20080291767A1
公开(公告)日：2008-11-27
申请号：US11751315
申请日：2007-05-21
申请人： Joseph S. Barnes , Jagreet S. Atwal , Kerry Bernstein , Robert J. Bucki
发明人： Joseph S. Barnes , Jagreet S. Atwal , Kerry Bernstein , Robert J. Bucki
IPC分类号： G11C8/00 , H01L21/4763
CPC分类号： H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203
摘要： A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stacked layer.
摘要翻译：提供多端口寄存器文件（例如，存储器元件），其中寄存器堆的每个读端口位于主数据存储元件上方和/或下方的单独晶片中。这在本发明中通过利用三维积分来实现，其中多个有源电路层被垂直堆叠并且使用垂直排列的互连将装置从堆叠层之一连接到另一层叠层中的另一装置。

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