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101. 发明授权

US5656518A Method for fabrication of a non-symmetrical transistor 失效
标题翻译：制造非对称晶体管的方法
公开(公告)号：US5656518A
公开(公告)日：1997-08-12
申请号：US713386
申请日：1996-09-13
申请人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/66659 , H01L29/7835
摘要： In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. The present invention includes a gate insulator and a gate electrode, such as a polysilicon, formed over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls. A first dopant is implanted to provide a lightly doped drain region substantially aligned with the second sidewall. An oxide layer provides first and second sidewall oxide regions adjacent the first and second sidewalls, respectively. The first sidewall oxide region is isolated using a nitride layer having a window which exposes the second sidewall oxide region. Thermal oxidation is applied to the second sidewall oxide region wherein the size of the second sidewall oxide region increases while the size of the first sidewall oxide region remains substantially constant. The first sidewall oxide region is then exposed by removing the nitride layer and a second dopant is implanted to provide a heavily doped drain region substantially aligned with the outside edge of the second sidewall oxide region and a heavily doped source region.
摘要翻译：在本发明中，描述了用于制造非对称LDD-IGFET的方法。本发明包括形成在半导体衬底上的栅极绝缘体和诸如多晶硅的栅电极，栅电极具有顶表面和相对的第一和第二侧壁。植入第一掺杂剂以提供基本上与第二侧壁对准的轻掺杂漏极区。氧化物层分别提供与第一和第二侧壁相邻的第一和第二侧壁氧化物区域。使用具有暴露第二侧壁氧化物区域的窗口的氮化物层来隔离第一侧壁氧化物区域。热氧化被施加到第二侧壁氧化物区域，其中第二侧壁氧化物区域的尺寸增加，而第一侧壁氧化物区域的尺寸保持基本恒定。然后通过去除氮化物层来暴露第一侧壁氧化物区域，并且注入第二掺杂剂以提供与第二侧壁氧化物区域的外边缘基本对准的重掺杂漏极区域和重掺杂源极区域。

102. 发明授权

US5445975A Semiconductor wafer with enhanced pre-process denudation and process-induced gettering 失效
标题翻译：半导体晶片具有增强的预处理剥蚀和工艺引起的吸气
公开(公告)号：US5445975A
公开(公告)日：1995-08-29
申请号：US206977
申请日：1994-03-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
IPC分类号： H01L21/322 , H01L21/324
CPC分类号： H01L21/3225 , Y10S148/06
摘要： A method is provided for pre-process denudation and process-induced gettering of a CZ silicon wafer having one or more monolithic devices embodied therein. Pre-process denudation is performed in a hydrogen ambient to out-diffuse oxygen as well as to maintain interstitial silicon flux away from the substrate surface. Process-induced gettering is performed at a low temperature to ensure stacking faults and surface irregularities do not arise from interstitial silicon bonding at the surface prior to gate oxidation. The third step of the denudation/gettering cycle involving precipitate growth is thereby delayed or forestalled until the field oxide is grown. Any changes or movement in oxygen and/or interstitial silicon within or near the substrate surface occurring after polysilicon deposition will have minimal effect upon the established gate oxide. Accordingly, gate oxide integrity (e.g., breakdown voltage and uniformity) are enhanced by the present process.
摘要翻译：提供了一种用于预处理剥蚀和具有其中实施的具有一个或多个单片器件的CZ硅晶片的工艺诱导吸除的方法。在氢环境中进行预处理剥蚀以使氧扩散以及保持间隙硅熔剂远离衬底表面。在低温下进行过程诱导的吸气以确保堆垛层错，并且在栅极氧化之前的表面处的间隙硅键不会产生表面不规则性。涉及沉淀生长的剥蚀/吸除循环的第三步骤因此被延迟或预防，直到场氧化物生长。在多晶硅沉积之后发生的衬底表面内或附近的氧和/或间隙硅中的任何变化或移动对所建立的栅极氧化物的影响最小。因此，通过本方法增强栅极氧化物完整性（例如，击穿电压和均匀性）。

103. 发明授权

US07544999B2 SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate 有权
标题翻译： SOI半导体器件在体硅衬底中具有增强的自对准电介质区域
公开(公告)号：US07544999B2
公开(公告)日：2009-06-09
申请号：US11072661
申请日：2005-03-04
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L29/78603
摘要： In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In further embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode.
摘要翻译：在一个说明性实施例中，该方法包括在由大量衬底，掩埋绝缘层和有源层组成的SOI衬底之上形成栅电极，该栅电极具有形成在其上的保护层，并且在该衬底中形成多个电介质区域在栅电极形成之后，电介质区域相对于栅电极自对准，介质区域的介电常数小于体基板的介电常数。在另外的实施例中，该方法包括在由大量衬底，掩埋绝缘层和有源层组成的SOI衬底之上形成栅电极，栅极具有形成在其上的保护层，在栅极之后执行至少一个氧注入工艺形成电极和保护层，以将氧原子引入本体衬底中，从而在本体衬底中形成多个氧掺杂区域，并且执行至少一个退火工艺以将氧掺杂区域转换成由硅构成的电介质区域散装衬底中的二氧化物。在一个说明性实施例中，该器件包括形成在SOI结构之上的栅电极，该SOI结构包括体衬底，掩埋绝缘层和有源层，以及由形成在本体衬底中的二氧化硅构成的多个电介质区域，区域相对于栅电极自对准。

104. 发明授权

US07129142B2 Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same 有权
公开(公告)号：US07129142B2
公开(公告)日：2006-10-31
申请号：US10167184
申请日：2002-06-11
申请人： Derick J. Wristers , Andy C. Wei , Mark B. Fuselier
发明人： Derick J. Wristers , Andy C. Wei , Mark B. Fuselier
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84
摘要： In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate in an area above the doped region and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product, the integrated circuit product being comprised of a plurality of transistors formed in an active layer of an SOI substrate above a doped region formed in a bulk substrate of the SOI substrate, the doped region being formed under the active layer, sensing an activity level of the integrated circuit product and applying a voltage of a magnitude and a polarity to the doped region, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product.

105. 发明授权

US06661057B1 Tri-level segmented control transistor and fabrication method 失效
标题翻译：三电平分段控制晶体管及其制造方法
公开(公告)号：US06661057B1
公开(公告)日：2003-12-09
申请号：US09056836
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L27088
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/32053 , H01L21/76802 , H01L21/76855 , H01L29/66484 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7833 , Y10S257/90
摘要： A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.
摘要翻译：晶体管形成在具有分段栅极结构的有源区中。分段栅结构有利地提供了在晶体管内形成的沟道区的动态控制。轻掺杂的源极和漏极（LDD）区域形成为与栅电极对准。在与栅电极的暴露表面相邻形成绝缘层之后，形成布置在LDD区域上方的导电间隔物。这些间隔物通过绝缘层与栅电极电隔离。形成重掺杂的源极和漏极（S / D）区域，其与间隔物对准，并且例如通过提供给导电间隔物，栅电极和S / D区域的自对准硅化物工艺进行电接触。所描述的结构有利地通过对S / D区域的LDD部分的动态独立控制来提供通道区域的动态控制。

106. 发明授权

US06589847B1 Tilted counter-doped implant to sharpen halo profile 有权
标题翻译：倾斜反掺杂植入物以锐化晕轮廓
公开(公告)号：US06589847B1
公开(公告)日：2003-07-08
申请号：US09631557
申请日：2000-08-03
申请人： Daniel Kadosh , Scott D. Luning , Derick J. Wristers
发明人： Daniel Kadosh , Scott D. Luning , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/1045 , H01L29/6656
摘要： The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and forming halo implant regions in the substrate adjacent the gate electrode by performing at least the following steps: performing a first angled implant process using a dopant material that is of a type opposite to the first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material. The method concludes with performing at least one additional implantation process to further form source/drain regions for the device.
摘要翻译：本发明涉及一种在半导体器件中形成卤素注入区的方法。在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，该衬底被掺杂有第一种类型的掺杂剂材料，以及通过至少执行以下步骤在邻近栅极的衬底中形成卤素注入区域：执行使用与第一类型的掺杂剂材料相反的类型的掺杂剂材料并使用与第一类型的掺杂剂材料具有相同类型的掺杂剂材料来执行第二成角度的注入的第一成角度注入工艺。该方法的结论是执行至少一个额外的注入工艺以进一步形成器件的源极/漏极区域。

107. 发明授权

US06410409B1 Implanted barrier layer for retarding upward diffusion of substrate dopant 失效
标题翻译：用于延缓衬底掺杂剂的向上扩散的植入阻挡层
公开(公告)号：US06410409B1
公开(公告)日：2002-06-25
申请号：US08741799
申请日：1996-10-31
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21265
CPC分类号： H01L21/8238 , H01L21/26506 , H01L21/26513 , H01L21/74
摘要： Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of the P+ layer and well below transistor source/drain regions. One embodiment includes a lightly doped epitaxial layer formed upon an underlying P+ substrate. In another embodiment, a deep boron implant forms a P+ layer within a P− substrate, and affords many of the advantages of an epitaxial layer without actually requiring such an epitaxial layer. The nitrogen implant is performed at a preferred energy of 1-3 MeV to form the implanted nitrogen barrier layer at a depth in the range of 1-5 microns. Oxygen may also be implanted to form a diffusion barrier layer to retard the upward diffusion of arsenic or phosphorus forming a deep N+ layer.
摘要翻译：在随后的热处理操作（例如退火）期间，在半导体衬底内形成深P +层的硼向上扩散。用于延迟硼的这种向上扩散的方法包括注入氮以在P +层的上边界附近形成氮阻挡层，并且远低于晶体管源/漏区。一个实施例包括形成在下面的P +衬底上的轻掺杂的外延层。在另一个实施例中，深硼注入在P-衬底内形成P +层，并提供外延层的许多优点，而不需要这样的外延层。以1-3MeV的优选能量进行氮注入，以在1-5微米范围内的深度形成注入的氮阻挡层。氧也可以被植入以形成扩散阻挡层，以阻止形成深N +层的砷或磷的向上扩散。

108. 发明授权

US06406964B1 Method of controlling junction recesses in a semiconductor device 有权
标题翻译：控制半导体器件中的接合凹部的方法
公开(公告)号：US06406964B1
公开(公告)日：2002-06-18
申请号：US09704008
申请日：2000-11-01
申请人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
发明人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/665 , H01L29/7833
摘要： The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implant process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.
摘要翻译：本发明涉及一种形成晶体管的方法。在一个实施例中，所述方法包括提供衬底，所述衬底被掺杂有第一类型的掺杂剂材料，在由所述隔离结构限定的所述衬底的有源区域中的所述衬底上形成晶体管，以及执行至少一个离子注入在与晶体管的栅电极相邻的衬底中注入掺杂剂原子的工艺。该方法还包括在晶体管上执行与第一类掺杂剂材料相反类型的掺杂剂材料的至少两个成角度的离子注入工艺，并执行至少一个退火工艺。

109. 发明授权

US06380055B2 Dopant diffusion-retarding barrier region formed within polysilicon gate layer 有权
标题翻译：在多晶硅栅极层内形成的掺杂扩散阻滞层
公开(公告)号：US06380055B2
公开(公告)日：2002-04-30
申请号：US09177043
申请日：1998-10-22
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L213205
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/32155
摘要： A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer. The thickness of the nitrogen-containing layer is preferably approximately 5-15 Å thick. Any nitrogen residing at the top of the gate dielectric may be kept to a concentration less than approximately 2%. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness of approximately 25-60 Å, when using a p-type dopant, such as boron.
摘要翻译：扩散阻滞屏障区域被结合到栅电极中以减少掺杂剂朝向栅极电介质的向下扩散。阻挡区域是在两个单独形成的多晶硅层之间形成的含氮扩散阻滞区域。多晶硅的上层比多晶硅的下层掺杂更多，并且势垒区域用于将大部分掺杂剂保持在多晶硅的上层内，并且还可以允许一些掺杂剂扩散到多晶硅的下层。阻挡区域可以例如通过在含氮环境中退火第一多晶硅层以在第一多晶硅层的顶表面处形成氮化层而形成。可以通过在第一多晶硅层的顶表面上沉积含氮层，例如氮化硅或氮化钛层来形成阻挡区。含氮层的厚度优选为约5〜约厚。驻留在栅极电介质顶部的任何氮可以保持在小于约2％的浓度。当使用诸如硼的p型掺杂剂时，本发明特别适用于薄栅极电介质，例如厚度大约为25埃的那些。

110. 发明授权

US06316302B1 Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant 有权
标题翻译：各向同性蚀刻要用于NMOS源极/漏极注入和PMOS LDD植入物的侧壁间隔物
公开(公告)号：US06316302B1
公开(公告)日：2001-11-13
申请号：US09604051
申请日：2000-06-26
申请人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
发明人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/823864 , H01L29/6656
摘要： A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
摘要翻译：提供了一种用于各向同性蚀刻侧壁间隔物对以减少每个侧壁间隔物的横向厚度的方法。在一个实施例中，第一和第二对侧壁间隔件同时形成在相应的第一和第二栅极导体的相对的侧壁表面上。第一和第二栅极导体分别在半导体衬底的隔离的第一和第二有源区域上横向间隔开。有利地，在形成PMOS晶体管的NMOS晶体管和LDD区域的源极和漏极区域期间，单个侧壁间隔物对被用作掩模结构。也就是说，在减少侧壁间隔物的横向厚度之前，n +源极/漏极（“S / D”）植入物在第一对侧壁间隔物的外侧边缘上自对准。然而，在间隔物厚度减小之后，p-LDD植入物自对准到第二对侧壁间隔物的外侧边缘。因此，不需要在栅极导体的侧壁表面附近形成多对侧壁间隔件，以改变注入区域和后续集成电路的栅极导体之间的间隔。

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