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101. 发明授权

US07772527B2 Heat reflector and substrate processing apparatus comprising the same 有权
标题翻译：热反射器和包括其的基板处理装置
公开(公告)号：US07772527B2
公开(公告)日：2010-08-10
申请号：US11405563
申请日：2006-04-18
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： F27B5/06 , F27B5/14 , F27D19/00 , F21V7/00 , F21V7/10 , F21V7/16
CPC分类号： H01L21/67115 , F27B5/04 , F27B17/0025 , Y10T428/24273
摘要： A substrate processing apparatus includes a process chamber including upper and lower quartz walls, a substrate support disposed in the process chamber, radiant heaters respectively provided above and below the quartz walls of the chamber, and heat reflectors disposed outside the process chamber for reflecting heat towards the substrate support. Each of the heat reflectors has heating has a first thermally reflective section oriented to reflect the heat towards an outer peripheral region of the substrate support and a second thermally reflective section oriented to reflect the heat towards a central region of the substrate support. Each heat reflector also has a reflection angle adjusting mechanism by which an angle at which the second thermally reflective section reflects heat can be adjusted. The angle is adjusted depending on the temperature distribution across the substrate so that the substrate can be processed uniformly.
摘要翻译：基板处理装置包括具有上，下石英壁的处理室，设置在处理室中的基板支撑件，分别设置在室的石英壁上方和下方的辐射加热器，以及设置在处理室外部的热反射器，用于将热量反射衬底支撑。每个热反射器具有加热，其具有第一热反射部分，其被定向成朝着基板支撑件的外周区域反射热量;以及第二热反射部件，其被定向成朝着基板支撑件的中心区域反射热量。每个热反射器还具有反射角调节机构，通过该反射角调节机构可以调节第二热反射部分反射热量的角度。根据衬底上的温度分布来调节角度，使得可以均匀地处理衬底。

102. 发明授权

US07750699B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07750699B2
公开(公告)日：2010-07-06
申请号：US12010964
申请日：2008-01-31
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/222 , H03L7/0805
摘要： A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a DLL clock having frozen locking information when exiting the power down mode. A controller precludes phase update operation of the DLL when a predetermined time passes after entering the power down mode to thereby obtain a time margin for a phase update operation undertaken in the normal mode.
摘要翻译： DLL电路和同步存储器件在功率下降模式下执行稳定的操作，尽管进入/退出掉电模式是快速重复的。同步存储器件在正常模式和掉电模式下工作。延迟锁定环（DLL）在退出掉电模式时产生具有冻结锁定信息的DLL时钟。当在进入掉电模式之后的预定时间过去时，控制器阻止DLL的相位更新操作，从而获得在正常模式下进行的相位更新操作的时间余量。

103. 发明授权

US07605622B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07605622B2
公开(公告)日：2009-10-20
申请号：US11478094
申请日：2006-06-30
申请人： Hoon Choi , Jae-Jin Lee
发明人： Hoon Choi , Jae-Jin Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F7/68 , H03L7/0805
摘要： A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.
摘要翻译：具有正常模式和掉电模式的存储器件的DLL包括用于缓冲外部时钟信号以输出内部时钟信号的时钟缓冲器。断电模式控制器响应于时钟使能信号产生掉电模式控制信号以定义正常模式或掉电模式。源时钟生成单元在停电模式控制信号的控制下接收内部时钟信号以产生DLL源时钟信号。相位更新单元基于DLL源时钟信号执行相位更新操作，以输出DLL时钟信号。

104. 发明申请

US20090178097A1 METHOD, APPARATUS AND SYSTEM FOR GENERATING AND FACILITATING MOBILE HIGH-DEFINITION MULTIMEDIA INTERFACE 有权
标题翻译：用于生成和促进移动高清晰度多媒体接口的方法，装置和系统
公开(公告)号：US20090178097A1
公开(公告)日：2009-07-09
申请号：US11969847
申请日：2008-01-04
申请人： Gyudong Kim , Baegin Sung , Hoon Choi
发明人： Gyudong Kim , Baegin Sung , Hoon Choi
IPC分类号： H04N7/173
CPC分类号： G06F3/14 , G06F13/4072 , G09G5/006 , G09G2370/045 , G09G2370/047 , H04L65/605
摘要： A method, apparatus and system are provided for generating and facilitating Mobile High-Definition Multimedia Interface. In one embodiment, an apparatus includes a transmitter configured to merge multiple channels of a high-definition interface into a single channel to generate a mobile high-definition interface, the mobile high-definition interface configured to facilitate carrying of high-definition media content in a mobile device. The apparatus further includes a receiver coupled with the transmitter, the receiver configured to receive the single channel, and to unmerge the single channel into the multiple channels.
摘要翻译：提供了一种用于生成和促进移动高分辨率多媒体接口的方法，装置和系统。在一个实施例中，一种装置包括：发射机，被配置为将高清晰度接口的多个信道合并成单个信道以产生移动高清晰度接口，所述移动高清晰度接口被配置为便于携带高清晰度媒体内容移动设备。所述设备还包括与所述发射机耦合的接收机，所述接收机被配置为接收所述单个信道，并且将所述单个信道解除合并到所述多个信道中。

105. 发明授权

US07528639B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US07528639B2
公开(公告)日：2009-05-05
申请号：US12071985
申请日：2008-02-28
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is enabled.
摘要翻译： DLL电路包括：缓冲器控制单元，被配置为检测DLL电源是否超过参考电平并输出缓冲器控制信号。当缓冲器控制信号使能时，时钟缓冲器缓冲外部时钟以产生内部时钟。

106. 发明授权

US07501866B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07501866B2
公开(公告)日：2009-03-10
申请号：US11477528
申请日：2006-06-30
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/222 , H03L7/0805
摘要： A synchronous memory device having a normal mode and a power down mode includes a power down mode controller for generating a power down mode control signal in response to a clock enable signal, thereby determining onset or termination of a power down mode. A clock buffering unit buffers an external clock signal in response to the power down mode control signal and outputs first and second internal clock signals. A clock selection unit selects one of the first and second internal clock signals based on the power down mode control signal to output the selected signal as an intermediate output clock signal. A phase update unit performs a phase update operation by using the intermediate output clock signal to output a delay locked loop (DLL) clock signal, the first internal clock signal differing in frequency from the second internal clock signal.
摘要翻译：具有正常模式和掉电模式的同步存储器件包括功率下降模式控制器，用于响应于时钟使能信号产生掉电模式控制信号，从而确定掉电模式的开始或结束。时钟缓冲单元响应于掉电模式控制信号缓冲外部时钟信号，并输出第一和第二内部时钟信号。时钟选择单元基于掉电模式控制信号选择第一和第二内部时钟信号中的一个，以输出所选择的信号作为中间输出时钟信号。相位更新单元通过使用中间输出时钟信号来执行相位更新操作，以输出与第二内部时钟信号不同频率的第一内部时钟信号的延迟锁定环（DLL）时钟信号。

107. 发明授权

US07352218B2 DLL circuit and method of controlling the same 有权
公开(公告)号：US07352218B2
公开(公告)日：2008-04-01
申请号：US11637757
申请日：2006-12-13
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is enabled.

108. 发明授权

US07236553B1 Reduced dead-cycle, adaptive phase tracking method and apparatus 有权
标题翻译：减少死循环，自适应相位跟踪方法和装置
公开(公告)号：US07236553B1
公开(公告)日：2007-06-26
申请号：US10763905
申请日：2004-01-23
申请人： Hoon Choi , Gyudong Kim , Daeyun Shim , Bruce Kim , Seung Ho Hwang
发明人： Hoon Choi , Gyudong Kim , Daeyun Shim , Bruce Kim , Seung Ho Hwang
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H04L7/0008
摘要： A data sampling method and circuit employing an oversampling clock to oversample a data signal, a phase tracker for use with or in a data sampling circuit, and a method for identifying a sequence of best sampling positions for sampling a data signal from signal samples generated using an oversampling clock. In some embodiments, data indicative of the phase of at least one of the oversampling clock's sampling positions relative to the center of the data eye are low-pass filtered in a manner determined by the data signal's bit rate. In other embodiments, the number of dead cycles of the phase tracker decision loop is reduced by generating possible solutions in parallel and moving the feedback point so as to occur as late as practical, or the phase tracker ignores a sample set when updating its determination of the best sampling position when the sample set indicates that the data signal has less than a predetermined number of transitions during a corresponding tracking period.
摘要翻译：使用过采样时钟对数据信号进行过采样的数据采样方法和电路，与数据采样电路一起使用或在数据采样电路中使用的相位跟踪器，以及用于识别最佳采样位置序列的方法，用于从使用过采样时钟。在一些实施例中，指示相对于数据眼睛的中心的过采样时钟的采样位置中的至少一个的相位的数据以由数据信号的比特率确定的方式进行低通滤波。在其他实施例中，相位跟踪器判定循环的死循环的数量通过并行产生可能的解并且将反馈点移动以便尽可能晚地发生而减少，或者当更新其样本集的确定时，相位跟踪器忽略样本集当样本集合表示在对应的跟踪周期期间数据信号具有小于预定数量的转换时的最佳采样位置。

109. 发明授权

US06969766B2 PNA monomer and precursor 有权
标题翻译： PNA单体和前体
公开(公告)号：US06969766B2
公开(公告)日：2005-11-29
申请号：US10424181
申请日：2003-04-25
申请人： Sung Kee Kim , Hyunil Lee , Jong Chan Lim , Hoon Choi , Jae Hoon Jeon , Sang Youl Ahn , Sung Hee Lee , Won Jun Yoon
发明人： Sung Kee Kim , Hyunil Lee , Jong Chan Lim , Hoon Choi , Jae Hoon Jeon , Sang Youl Ahn , Sung Hee Lee , Won Jun Yoon
IPC分类号： C12N15/09 , A61K31/513 , A61K31/52 , C07D277/80 , C07D405/12 , C07D417/04 , C07D417/12 , C07D417/14 , C07D473/02 , C07D473/18 , C07D473/32 , C07D473/34 , C07D247/02 , C07D413/12
CPC分类号： C07D417/04 , C07B2200/11 , C07D277/80 , C07D417/12 , C07D417/14 , Y02P20/55
摘要： This application relates to monomers of the general formula (I) for the preparation of PNA (peptide nucleic acid) oligomers and provides method for the synthesis of both predefined sequence PNA oligomers and random sequence PNA oligomers: wherein E is nitrogen or C—R′; J is sulfur or oxygen; R′, R1, R2, R3, R4 is independently H, halogen, alkyl, nitro, nitrile, alkoxy, halogenated alkyl, halogenated alkoxy, phenyl or halogenated phenyl, R5 is H or protected or unprotected side chain of natural or unnatural α-amino acid; and B is a natural or unnatural nucleobase, wherein when said nucleobase has an exocyclic amino function, said function is protected by protecting group which is labile to acids but stable to weak to medium bases in the presence of thiol.
摘要翻译：本申请涉及用于制备PNA（肽核酸）寡聚体的通式（I）的单体，并提供合成预定义的序列PNA寡聚体和随机序列PNA寡聚体的方法：其中E为氮或C-R' ; J为硫或氧; R'，R 1，R 2，R 3，R 4独立地是H，卤素，烷基，硝基，腈，烷氧基，卤代烷基，卤代烷氧基，苯基或卤代苯基，R 5是H或被保护或未被保护的天然或非天然α- 氨基酸; 并且B是天然或非天然核碱基，其中当所述核碱基具有环外氨基功能时，所述功能受到在硫醇存在下对酸不稳定但对弱至中碱稳定的保护基保护。

110. 发明授权

US06560679B2 Method and apparatus for reducing power consumption by skipping second accesses to previously accessed cache lines 失效
标题翻译：通过跳过对先前访问的高速缓存行的第二次访问来降低功耗的方法和装置
公开(公告)号：US06560679B2
公开(公告)日：2003-05-06
申请号：US09742030
申请日：2000-12-20
申请人： Hoon Choi , Myung-Kyoon Yim
发明人： Hoon Choi , Myung-Kyoon Yim
IPC分类号： G06F1208
CPC分类号： G06F12/0882 , G06F12/0862 , G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory. The controller stores state information on access type, operation mode and cache hit/miss associated with the most recent access to the tag RAM, and controls a current access to the tag RAM just after the preceding access based on the state information and a portion of a set field of a main memory address for the second access. The controller determines whether the current access is applied to the same cache line that was accessed in the first access based on the state information and a portion of a set field of the main memory address for the second access, and allows the current access to be skipped when the current access is applied to the same cache line that was accessed in the preceding access.
摘要翻译：提供了一种数字数据处理系统，其包括数字数据处理器，具有标签RAM和数据RAM的高速缓冲存储器，以及用于控制对高速缓存存储器的访问的控制器。控制器存储关于与最近访问标签RAM相关联的访问类型，操作模式和高速缓存命中/错误的状态信息，并且基于状态信息控制刚刚在上述访问之后的标签RAM的当前访问用于第二次访问的主存储器地址的设置字段。控制器基于状态信息和用于第二次访问的主存储器地址的设置字段的一部分来确定当前访问是应用于在第一访问中访问的相同高速缓存行，并且允许当前访问是当当前访问应用于在上一次访问中访问的同一个高速缓存行时跳过。

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