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101. 发明授权

US08324031B2 Diffusion barrier and method of formation thereof 有权
标题翻译：扩散屏障及其形成方法
公开(公告)号：US08324031B2
公开(公告)日：2012-12-04
申请号：US12144652
申请日：2008-06-24
申请人： Shyue Seng Tan , Lee Wee Teo , Yung Fu Chong , Elgin Quek , Sanford Chu
发明人： Shyue Seng Tan , Lee Wee Teo , Yung Fu Chong , Elgin Quek , Sanford Chu
IPC分类号： H01L21/00
CPC分类号： H01L29/66537 , H01L21/26506 , H01L21/266 , H01L21/3223 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L23/532 , H01L27/088 , H01L29/0649 , H01L29/1083 , H01L29/32 , H01L29/36 , H01L29/66477 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
摘要翻译：提出了一种形成装置的方法。该方法包括提供具有第一和第二区域的结构。在第一和第二区域的至少一部分之间形成扩散阻挡层。扩散屏障包括减少元件在第一和第二区域之间的扩散的空腔。

102. 发明申请

US20120292707A1 NANO-ELECTRO-MECHANICAL SYSTEM (NEMS) STRUCTURES ON BULK SUBSTRATES 有权
标题翻译：纳米电子机械系统（NEMS）结构在大块基板上
公开(公告)号：US20120292707A1
公开(公告)日：2012-11-22
申请号：US13108439
申请日：2011-05-16
申请人： Eng Huat Toh , Elgin Quek , Chung Foong Tan
发明人： Eng Huat Toh , Elgin Quek , Chung Foong Tan
IPC分类号： H01L21/336 , H01L29/78 , B82Y99/00
CPC分类号： H01L29/685 , B81B3/0081 , B81B2203/0109 , B81B2207/015 , B82Y10/00 , G11C11/56 , G11C23/00 , G11C2213/16 , H01L21/28282 , H01L21/764 , H01L27/1052 , H01L27/10826 , H01L27/10879 , H01L27/10894 , H01L27/1104 , H01L27/11573 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： Semiconductor devices are formed with a nano-electro-mechanical system (NEMS) logic or memory on a bulk substrate. Embodiments include forming source/drain regions directly on a bulk substrate, forming a fin connecting the source/drain regions, forming two gates, one on each side of the fin, the two gates being insulated from the bulk substrate, and forming a substrate gate in the bulk substrate. The fin is separated from each of the two gates and the substrate gate with an air gap.
摘要翻译：半导体器件由体积衬底上的纳米机电系统（NEMS）逻辑或存储器形成。实施例包括直接在体基板上形成源极/漏极区域，形成连接源极/漏极区域的鳍片，形成两个栅极，鳍片的每一侧上一个，两个栅极与本体衬底绝缘，以及形成衬底栅极在散装衬底中。翅片与具有气隙的两个栅极和衬底栅极中的每一个分离。

103. 发明申请

US20120228705A1 LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
标题翻译： LDMOS具有改进的断电电压
公开(公告)号：US20120228705A1
公开(公告)日：2012-09-13
申请号：US13046332
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/42364 , H01L29/42368 , H01L29/42372 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层，第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

104. 发明申请

US20120228695A1 LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 有权
标题翻译： LDMOS具有改进的断电电压
公开(公告)号：US20120228695A1
公开(公告)日：2012-09-13
申请号：US13046313
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/42368 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层，分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成栅极堆叠彼此分离并具有不同的栅极电介质材料。

105. 发明授权

US08008744B2 Selective STI stress relaxation through ion implantation 有权
标题翻译：通过离子注入选择性STI应力松弛
公开(公告)号：US08008744B2
公开(公告)日：2011-08-30
申请号：US12790975
申请日：2010-05-31
申请人： Lee Wee Teo , Shiang Yang Ong , Jae Gon Lee , Vincent Leong , Elgin Quek , Dong Kyun Sohn
发明人： Lee Wee Teo , Shiang Yang Ong , Jae Gon Lee , Vincent Leong , Elgin Quek , Dong Kyun Sohn
IPC分类号： H01L21/36
CPC分类号： H01L27/092 , H01L21/31155 , H01L21/76224 , H01L21/823807 , H01L29/6659 , H01L29/7846
摘要： A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.
摘要翻译：第一示例性实施例包括以下步骤和由其形成的结构。在衬底内形成具有相对侧壁的沟槽。在相对的沟槽侧壁上形成具有固有应力的应力层。应力层在沟槽侧壁上具有应力层侧壁。将离子注入应力层的一个或多个部分以形成离子注入的松弛部分，其中未注入的应力层的部分是未注入的部分，由此一个或多个离子注入的松弛部分的固有应力的应力层部分被松弛。

106. 发明申请

US20100315884A1 Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof 有权
标题翻译：利用冲击电离和隧穿的非易失性存储器及其制造方法
公开(公告)号：US20100315884A1
公开(公告)日：2010-12-16
申请号：US12456440
申请日：2009-06-16
申请人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
发明人： Eng Huat Toh , Chung Foong Tan , Shyue Seng Tan , Jae Gon Lee , Elgin Quek
IPC分类号： G11C16/04 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7885 , G11C16/0408 , H01L29/42336 , H01L29/66825
摘要： A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.
摘要翻译：公开并构造了非易失性存储器件（和制造方法），以使得能够在器件的第一部分中使用电离冲击处理的写入操作以及在器件的第二部分中使用隧道工艺的读取操作。非易失性存储器件（1）增加了热载流子注入效率，（2）降低功耗，（3）使非易失性存储器件中的电压和器件缩放。

107. 发明申请

US20070141775A1 Modulation of stress in stress film through ion implantation and its application in stress memorization technique 审中-公开
标题翻译：通过离子注入调制应力薄膜中的应力及其在应力记忆技术中的应用
公开(公告)号：US20070141775A1
公开(公告)日：2007-06-21
申请号：US11304412
申请日：2005-12-15
申请人： Lee Teo , Elgin Quek
发明人： Lee Teo , Elgin Quek
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864
摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.
摘要翻译：本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。对应力层进行重离子注入，然后进行退火。这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

108. 发明授权

US07071069B2 Shallow amorphizing implant for gettering of deep secondary end of range defects 失效
标题翻译：浅非晶化植入物用于吸收深度范围缺陷的二次端
公开(公告)号：US07071069B2
公开(公告)日：2006-07-04
申请号：US10743247
申请日：2003-12-22
申请人： Chung Foong Tan , Hyeokjae Lee , Eng Fong Chor , Elgin Quek
发明人： Chung Foong Tan , Hyeokjae Lee , Eng Fong Chor , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6656
摘要： A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.
摘要翻译：口袋植入法减少缺陷。我们在掺杂有第一导电类型掺杂剂的半导体衬底上提供栅极结构。我们执行口袋非晶化植入程序以形成与栅极结构相邻的凹穴注入区域和无定形凹穴区域。接下来，我们执行浅非晶化植入物以形成无定形浅植入区域。非晶浅植入区域形成在无定形袋区域上方的第二深度处。非晶浅植入区域之上的衬底优选保持结晶。我们执行S / D植入程序以形成深S / D区域。我们执行优选由第一浸泡步骤和第二尖峰步骤组成的退火程序，以重结晶非晶浅注入区域和非晶质凹槽区域。由浅的非晶态植入物减少由凹穴注入产生的缺陷。

109. 发明申请

US20050136623A1 Shallow amorphizing implant for gettering of deep secondary end of range defects 失效
标题翻译：浅非晶化植入物用于吸收深度范围缺陷的二次端
公开(公告)号：US20050136623A1
公开(公告)日：2005-06-23
申请号：US10743247
申请日：2003-12-22
申请人： Chung Tan , Hyeokjae Lee , Eng Chor , Elgin Quek
发明人： Chung Tan , Hyeokjae Lee , Eng Chor , Elgin Quek
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L21/322
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6656
摘要： A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.
摘要翻译：口袋植入法减少缺陷。我们在掺杂有第一导电类型掺杂剂的半导体衬底上提供栅极结构。我们执行口袋非晶化植入程序以形成与栅极结构相邻的凹穴注入区域和无定形凹穴区域。接下来，我们执行浅非晶化植入物以形成无定形浅植入区域。非晶浅植入区域形成在无定形袋区域上方的第二深度处。非晶浅植入区域之上的衬底优选保持结晶。我们执行S / D植入程序以形成深S / D区域。我们执行优选由第一浸泡步骤和第二尖峰步骤组成的退火程序，以重结晶非晶浅注入区域和非晶质凹槽区域。由浅的非晶态植入物减少由凹穴注入产生的缺陷。

110. 发明申请

US20050026337A1 THYRISTOR-BASED SRAM AND METHOD FOR THE FABRICATION THEREOF 失效
标题翻译：基于THYRISTOR的SRAM及其制造方法
公开(公告)号：US20050026337A1
公开(公告)日：2005-02-03
申请号：US10628912
申请日：2003-07-28
申请人： Elgin Quek , Pradeep Ramachandramurthy Yelehanka , Jia Zheng , Tommy Lai , Weining Li
发明人： Elgin Quek , Pradeep Ramachandramurthy Yelehanka , Jia Zheng , Tommy Lai , Weining Li
IPC分类号： H01L21/332 , H01L21/8244 , H01L27/11
CPC分类号： H01L29/66393 , H01L27/11
摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P—N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.
摘要翻译：一种用于制造集成电路结构的方法包括提供半导体衬底并在其上形成晶闸管。晶闸管具有至少四层，其间具有三个P-N结。至少两层是水平形成的，并且至少两层是垂直形成的。在至少一个垂直形成的层之间形成栅极。在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

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