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101. 发明申请

US20070044053A1 Multimode delay analyzer 失效
标题翻译：多模延迟分析仪
公开(公告)号：US20070044053A1
公开(公告)日：2007-02-22
申请号：US11205365
申请日：2005-08-17
申请人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
发明人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.
摘要翻译：一种分析集成电路设计中的多模延迟的方法，通过输入集成电路设计的网络列表，IO弧延迟，互连电弧延迟和具有分配布尔函数的恒定网络来生成集成电路设计的定时模型，传播恒定网络和布尔条件给IO弧延迟和互连电弧延迟，评估集成电路设计的定时路径延迟和条件，创建集成电路设计时序模型参数，并输出集成电路设计时序模型。该方法对于具有非常复杂的混合逻辑（包括时钟复用）的网表来说是特别需要的。特别地，RRAM是这样的网表。

102. 发明授权

US07181563B2 FIFO memory with single port memory modules for allowing simultaneous read and write operations 有权
标题翻译：具有单端口存储器模块的FIFO存储器，用于允许同时的读写操作
公开(公告)号：US07181563B2
公开(公告)日：2007-02-20
申请号：US10692664
申请日：2003-10-23
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F12/00
CPC分类号： G06F12/06 , G06F5/14 , G06F5/16
摘要： The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.
摘要翻译：本发明涉及具有单端口存储器模块的FIFO存储器，其可以允许同时的读和写操作。在本发明的示例性方面，一种采用具有半容量的单端口存储器模块的FIFO存储器来执行同时读和写操作的方法包括以下步骤：（a）提供用于偶数地址的第一单端口存储器模块的读或写操作; （b）提供用于读或写操作的奇数地址的第二单端口存储器模块; （c）交替地址和奇地址; 和（d）当读请求和写请求都在时钟周期到达第一单端口存储器模块或第二单端口存储器模块时，在当前时钟周期满足读请求并在下一个时刻满足写请求时钟周期。

103. 发明授权

US07111264B2 Process and apparatus for fast assignment of objects to a rectangle 有权
标题翻译：将对象快速分配给矩形的过程和设备
公开(公告)号：US07111264B2
公开(公告)日：2006-09-19
申请号：US10688460
申请日：2003-10-17
申请人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
发明人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.
摘要翻译：通过将矩形划分为多个较小的矩形并将对象分配过程（例如Kuhn算法）应用于每个第二矩形中的初始分配对象，将对象分配给矩形中的点。通过计算对象到点的分配的最大成本并且选择具有最大成本的最小值的对象的分配来执行初始分配，通过基于最小和最大成本之间的中点迭代地重新计算最大匹配分配来识别。

104. 发明授权

US07096413B2 Decomposer for parallel turbo decoding, process and integrated circuit 有权
标题翻译：并行turbo解码，处理和集成电路的分解器
公开(公告)号：US07096413B2
公开(公告)日：2006-08-22
申请号：US10299270
申请日：2002-11-19
申请人： Alexander E. Andreev , Ranko Scepanovic , Vojislav Vukovic
发明人： Alexander E. Andreev , Ranko Scepanovic , Vojislav Vukovic
IPC分类号： H03M13/03 , G06F11/00
CPC分类号： H03M13/6505 , H03M13/27 , H03M13/2957 , H03M13/6566
摘要： A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.
摘要翻译：用于存储在n个存储器中的访问数据的解码器包括在唯一坐标处包含存储器位置的地址的函数矩阵。分解器从第一和第二m×n矩阵的坐标位置排序地址，使得每行包含来自同一存储器的不超过一个地址。位置装置存储识别功能矩阵中地址的坐标的第三和第四m×n矩阵中的条目，使得第三矩阵中的每个条目在与第一矩阵中的对应坐标匹配的坐标处，并且第四矩阵中的每个条目在匹配的坐标处第二个矩阵中的对应坐标。解码器响应于矩阵中的条目，用于从存储器并行访问数据。

105. 发明授权

US07003510B2 Table module compiler equivalent to ROM 有权
公开(公告)号：US07003510B2
公开(公告)日：2006-02-21
申请号：US10177591
申请日：2002-06-19
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： H03K19/20 , G06F17/50 , G06F17/30
CPC分类号： G06F17/5045 , Y10S707/99933
摘要： A method of constructing a circuit for a Boolean function includes receiving as input a Boolean function of a number n of input variables wherein the number n of input variables may be varied over a range; generating at least two intermediate functions comprising sub-functions of the Boolean function wherein zero or one is substituted for all but two of the number n of input variables; and generating a selected output of the Boolean function of the number n of input variables from only two of the intermediate functions.

106. 发明申请

US20050091465A1 FIFO memory with single port memory modules for allowing simultaneous read and write operations 有权
标题翻译：具有单端口存储器模块的FIFO存储器，用于允许同时的读写操作
公开(公告)号：US20050091465A1
公开(公告)日：2005-04-28
申请号：US10692664
申请日：2003-10-23
申请人： Alexander Andreev , Anatoli Bolotov , Ranko Scepanovic
发明人： Alexander Andreev , Anatoli Bolotov , Ranko Scepanovic
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F12/06 , G06F5/14 , G06F5/16
摘要： The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.
摘要翻译：本发明涉及具有单端口存储器模块的FIFO存储器，其可以允许同时的读和写操作。在本发明的示例性方面，一种采用具有半容量的单端口存储器模块的FIFO存储器来执行同时读和写操作的方法包括以下步骤：（a）提供用于偶数地址的第一单端口存储器模块的读或写操作; （b）提供用于读或写操作的奇数地址的第二单端口存储器模块; （c）交替地址和奇地址; 和（d）当读请求和写请求都在时钟周期到达第一单端口存储器模块或第二单端口存储器模块时，在当前时钟周期满足读请求并在下一个时刻满足写请求时钟周期。

107. 发明申请

US20050030067A1 Universal gates for ICs and transformation of netlists for their implementation 失效
标题翻译： IC的通用门户，以及网路数据库的实施转型
公开(公告)号：US20050030067A1
公开(公告)日：2005-02-10
申请号：US10633856
申请日：2003-08-04
申请人： Alexander Andreev , Ranko Scepanovic
发明人： Alexander Andreev , Ranko Scepanovic
IPC分类号： G06F17/50 , H03D1/00
CPC分类号： G06F17/505
摘要： An original netlist is transformed to one employing universal gates. A negation net is created for each net coupled to an input or output of each gate and an input of each inverter in the original net. Each gate is removed from the original netlist and a universal gate is inserted so that the nets previously coupled to the inputs and output of the removed gate and a negation of those nets are coupled to the inputs and outputs of the inserted universal gate in a selected arrangement. Each inverter is removed from the original netlist and the net previously coupled to the input of the inverter is negated. A universal gate comprises gates performing anding and oring functions whose inputs and outputs are selectively coupled to the nets of the original netlist, and their negations.
摘要翻译：一个原始网表被转换为一个采用通用门。针对耦合到每个门的输入或输出的每个网络以及原始网络中每个逆变器的输入产生一个否定网。每个门从原始网表移除，并且插入通用门，使得先前耦合到被去除的门的输入和输出的网络以及这些网络的否定被耦合到所选择的插入的通用门的输入和输出安排。每个逆变器从原始网表中移除，并且先前耦合到逆变器输入端的网络被否定。通用门包括执行输入和输出功能的门，其输入和输出选择性地耦合到原始网表的网络，以及它们的否定。

108. 发明授权

US06536027B1 Cell pin extensions for integrated circuits 失效
标题翻译：集成电路的单元针扩展
公开(公告)号：US06536027B1
公开(公告)日：2003-03-18
申请号：US09735837
申请日：2000-12-13
申请人： Mikhail I. Grinchuk , Alexander E. Andreev , Ranko Scepanovic
发明人： Mikhail I. Grinchuk , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A metal wire for a feature of a cell is extended using a grid based on a metal layer of the cell. Each grid element is assigned an “F” designator representing the metal wire being extended, an “E” designator representing blockages to extension of the metal wire, such as metal wires of other features, or a “U” designator representing grid elements that are neither F-designated, nor E-designated grid elements. U-designated grid elements that are neighbors to E-designated grid elements are identified. A minimum length path is defined through the U-designated grid elements that are not neighbors to E-designated grid elements between the cell boundary and a F-designated grid element.
摘要翻译：使用基于电池的金属层的栅格来延长用于电池特征的金属线。每个网格元素被分配一个表示正在扩展的金属线的“F”指示符，表示阻止金属线延伸的“E”指示符，例如其他特征的金属线，或表示网格元素的“U” F指定，E指定网格元素。与E指定的网格元素相邻的U指定网格元素被识别。通过U指定的网格元素定义最小长度路径，该网格元素不是单元格边界和F指定的网格元素之间的E指定网格元素的邻居。

109. 发明授权

US06519746B1 Method and apparatus for minimization of net delay by optimal buffer insertion 有权
标题翻译：通过最佳缓冲区插入最小化净延迟的方法和装置
公开(公告)号：US06519746B1
公开(公告)日：2003-02-11
申请号：US09685990
申请日：2000-10-10
申请人： Alexander Andreev , Ranko Scepanovic , Anatoli Bolotov
发明人： Alexander Andreev , Ranko Scepanovic , Anatoli Bolotov
IPC分类号： G06F945
CPC分类号： G06F17/505
摘要： The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.
摘要翻译：本发明涉及一种减少网络延迟的方法。该方法包括构建时空网格，所述时间网格对应于网络，将波通过时空网格，所述波具有波值，并在所述时空网格上的点处插入缓冲器其中缓冲器的插入增加波值。缓冲区可以是负缓冲区或正缓冲区。通常，第二波与第一波同时通过时空网格。通常，第二波和第一波反转。

110. 发明授权

US06292924B1 Modifying timing graph to avoid given set of paths 失效
标题翻译：修改时序图以避免给定的路径集
公开(公告)号：US06292924B1
公开(公告)日：2001-09-18
申请号：US08964997
申请日：1997-11-05
申请人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
发明人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph. To avoid the false paths, the timing graph representing the circuit is modified to exclude the false paths before the graph is analyzed. To modify the timing graph, duplicate nodes are constructed, duplicate edges are constructed, and some edges of the original graph are cut and replaced by mixed edges connecting non-duplicate nodes to duplicate nodes. Finally, mixed edges are created to connect duplicate nodes to non-duplicate nodes, integrating the duplicate graph with the original graph.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 IC的设计需要满足实际的限制，例如最小化电路面积，最小化电路内的电线长度，以及使IC执行其功能所需的时间最小化，称为IC延迟。为了设计电路以满足给定的一组要求，必须分析电路的每个信号路径。由于大量的单元和复杂的连接，路径数量非常多，需要很多计算能力进行分析。此外，一些路径对于芯片的操作的目的不重要，并且可以在分析过程期间被折扣。本发明公开了一种用于避免分析非重要路径的方法和装置，被称为定向定时图的假路径。为了避免错误路径，修改表示电路的时序图，以排除图表分析之前的虚假路径。为了修改时序图，构造了重复的节点，构建了重复的边，原始图的一些边被剪切，并将不重复的节点连接到重复节点的混合边替换。最后，创建混合边以将重复节点连接到非重复节点，将重复图与原始图集成。

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