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1. 发明授权

US06292924B1 Modifying timing graph to avoid given set of paths 失效
标题翻译：修改时序图以避免给定的路径集
公开(公告)号：US06292924B1
公开(公告)日：2001-09-18
申请号：US08964997
申请日：1997-11-05
申请人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
发明人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph. To avoid the false paths, the timing graph representing the circuit is modified to exclude the false paths before the graph is analyzed. To modify the timing graph, duplicate nodes are constructed, duplicate edges are constructed, and some edges of the original graph are cut and replaced by mixed edges connecting non-duplicate nodes to duplicate nodes. Finally, mixed edges are created to connect duplicate nodes to non-duplicate nodes, integrating the duplicate graph with the original graph.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 IC的设计需要满足实际的限制，例如最小化电路面积，最小化电路内的电线长度，以及使IC执行其功能所需的时间最小化，称为IC延迟。为了设计电路以满足给定的一组要求，必须分析电路的每个信号路径。由于大量的单元和复杂的连接，路径数量非常多，需要很多计算能力进行分析。此外，一些路径对于芯片的操作的目的不重要，并且可以在分析过程期间被折扣。本发明公开了一种用于避免分析非重要路径的方法和装置，被称为定向定时图的假路径。为了避免错误路径，修改表示电路的时序图，以排除图表分析之前的虚假路径。为了修改时序图，构造了重复的节点，构建了重复的边，原始图的一些边被剪切，并将不重复的节点连接到重复节点的混合边替换。最后，创建混合边以将重复节点连接到非重复节点，将重复图与原始图集成。

2. 发明授权

US07856577B2 Command language for memory testing 有权
标题翻译：内存测试的命令语言
公开(公告)号：US07856577B2
公开(公告)日：2010-12-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F11/00
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

3. 发明授权

US07231383B2 Search engine for large-width data 有权
标题翻译：大型数据搜索引擎
公开(公告)号：US07231383B2
公开(公告)日：2007-06-12
申请号：US10137874
申请日：2002-05-01
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F17/30 , G06F15/16
CPC分类号： G06F9/342 , Y10S707/99931 , Y10S707/99933 , Y10S707/99934
摘要： A search engine architecture substitutes short indices for large data widths, thereby reducing widths required for input to and output from the search engine. The search engine system comprises a search engine responsive to an input address to access an index in the search engine. The index has a width no greater than logarithm on base 2 of the search engine capacity, thereby permitting the search engine to be embodied in an IC chip of reduced area. A driver responds to input commands and to the search engine status to manage indices in the search engine and enable the memory to access its addressable locations based on indices in the search engine.
摘要翻译：搜索引擎架构将短索引替换为大数据宽度，从而减少输入到搜索引擎输出所需的宽度。搜索引擎系统包括响应于输入地址以访问搜索引擎中的索引的搜索引擎。该索引具有不大于搜索引擎容量的基础2上的对数的宽度，从而允许搜索引擎体现在缩小区域的IC芯片中。驱动程序响应输入命令和搜索引擎状态来管理搜索引擎中的索引，并使内存能够基于搜索引擎中的索引访问其可寻址位置。

4. 发明授权

US06662287B1 Fast free memory address controller 失效
标题翻译：快速可用内存地址控制器
公开(公告)号：US06662287B1
公开(公告)日：2003-12-09
申请号：US10000243
申请日：2001-10-18
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F1200
CPC分类号： G06F12/023 , Y10S707/99953 , Y10S707/99956
摘要： A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.
摘要翻译：用于管理存储器中的地址分配的存储器管理器被构造为具有顶部顶点，底部水平和至少一个中间水平的分层树。底层包含多个底部顶点，每个底部顶点包含多个存储器中相应地址的自由或取代状态的表示。每个中间体包含至少一个包含多个标签的层次顶点，使得每个标签与子顶点相关联，并且定义包含相应子顶点的路径是否包含在包含至少一个自由表示的相应底层顶点中。一个分配命令将第一个自由地址的表示更改为Taken，一个free命令将指定地址的表示更改为Free。更改层次顶点中的标签以反映底层顶点的路径条件。

5. 发明授权

US08132075B2 Memory mapping for parallel turbo decoding 失效
标题翻译：并行turbo解码的内存映射
公开(公告)号：US08132075B2
公开(公告)日：2012-03-06
申请号：US11924385
申请日：2007-10-25
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译：路由复用器系统基于所选择的p个输入的排列来提供p个输出。多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。多个控制位表各自包含基于相应置换的布置中的多个位。存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。

6. 发明授权

US07216278B2 Method and BIST architecture for fast memory testing in platform-based integrated circuit 有权
标题翻译：方法和BIST架构，用于基于平台的集成电路中的快速内存测试
公开(公告)号：US07216278B2
公开(公告)日：2007-05-08
申请号：US10999493
申请日：2004-11-30
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/26 , G11C2029/2602
摘要： The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
摘要翻译：本发明提供了一种用于基于平台的集成电路中的快速存储器测试的方法和BIST架构。该方法可以包括以下步骤。启动Mem-BIST控制器发送器，使用确定性和无条件测试算法为平台中的存储器生成输入信号。输入信号被第一组管道延迟了n个时钟周期。延迟的输入信号由存储器接收，并且由存储器产生输出信号。输出信号被第二个流水线延迟了m个时钟周期。启动Mem-BIST控制器接收器以接收延迟的输出信号进行比较。

7. 发明申请

US20090133003A1 COMMAND LANGUAGE FOR MEMORY TESTING 有权
标题翻译：用于记忆测试的命令语言
公开(公告)号：US20090133003A1
公开(公告)日：2009-05-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F9/45
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

8. 发明授权

US07181563B2 FIFO memory with single port memory modules for allowing simultaneous read and write operations 有权
标题翻译：具有单端口存储器模块的FIFO存储器，用于允许同时的读写操作
公开(公告)号：US07181563B2
公开(公告)日：2007-02-20
申请号：US10692664
申请日：2003-10-23
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F12/00
CPC分类号： G06F12/06 , G06F5/14 , G06F5/16
摘要： The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.
摘要翻译：本发明涉及具有单端口存储器模块的FIFO存储器，其可以允许同时的读和写操作。在本发明的示例性方面，一种采用具有半容量的单端口存储器模块的FIFO存储器来执行同时读和写操作的方法包括以下步骤：（a）提供用于偶数地址的第一单端口存储器模块的读或写操作; （b）提供用于读或写操作的奇数地址的第二单端口存储器模块; （c）交替地址和奇地址; 和（d）当读请求和写请求都在时钟周期到达第一单端口存储器模块或第二单端口存储器模块时，在当前时钟周期满足读请求并在下一个时刻满足写请求时钟周期。

9. 发明授权

US07305593B2 Memory mapping for parallel turbo decoding 失效
标题翻译：并行turbo解码的内存映射
公开(公告)号：US07305593B2
公开(公告)日：2007-12-04
申请号：US10648038
申请日：2003-08-26
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F11/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译：路由多路复用器系统基于所选择的p个输入的排列来提供p个输出。多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。多个控制位表各自包含基于相应置换的布置中的多个位。存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。

10. 发明授权

US06886088B2 Memory that allows simultaneous read requests 失效
标题翻译：允许同时读取请求的内存
公开(公告)号：US06886088B2
公开(公告)日：2005-04-26
申请号：US10308334
申请日：2002-12-03
申请人： Egor A. Andreev , Anatoli A. Bolotov , Ranko Scepanovic , Alexander E. Andreev
发明人： Egor A. Andreev , Anatoli A. Bolotov , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F12/00 , G06F13/00 , G11C5/00
CPC分类号： G11C5/00 , G11C5/04 , G11C7/22 , G11C2207/2209
摘要： The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.
摘要翻译：本发明涉及允许具有改进的密度的两个同时读取请求的存储器。在本发明的一个方面，存储器模块包括至少两个主存储器子模块和附加的存储器子模块，该附加存储器子模块包括位于相应地址处的至少两个主存储器子模块中的值之和。附加存储器模块的总和使得能够执行至少两个同时的读取请求。

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