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101. 发明授权

US5745404A ISRAM layout and structure 失效
标题翻译： ISRAM布局和结构
公开(公告)号：US5745404A
公开(公告)日：1998-04-28
申请号：US567443
申请日：1995-12-05
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L27/11 , G11C11/00
CPC分类号： H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.
摘要翻译：三重多工艺形成具有紧凑的四晶体管SRAM单元布局的静态随机存取存储器（SRAM）。单元格布局在三层多晶硅之间划分结构，以减少每个单元所需的面积。此外，形成在上多晶硅层中的上拉电阻器之间的接触形成“捆扎”，通过该接头将栅极区域和穿通通孔下方的漏极区域交叉。上拉电阻延伸到单元区域的边界，以增加上拉电阻的长度和电阻。

102. 发明授权

US5693975A Compact P-channel/N-channel transistor structure 失效
标题翻译：紧凑的P沟道/ N沟道晶体管结构
公开(公告)号：US5693975A
公开(公告)日：1997-12-02
申请号：US539805
申请日：1995-10-05
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/06 , H01L27/11 , H01L29/04 , H01L29/76
CPC分类号： H01L27/0928 , H01L21/823814 , H01L21/823878 , Y10S257/903
摘要： A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another. The buried dielectric region underlies the two drain regions and contacts portions of both drain regions so as to (a) isolate the first drain region from the second body region and (b) isolate the second drain region from the first body region. The transistor structure can be fabricated according to processes in which formation of the body regions is initiated before or after the dielectric region is formed.
摘要翻译：互补场效应晶体管的结构包括具有第一导电类型的第一体区和相对的第二导电类型的邻接的第二体区的半导体本体。掩埋介电区位于半导体本体的下半导体表面下方并延伸到第一和第二体区内。第二导电类型的第一漏极区位于半导体本体中并与第一体区，电介质区和上半导体表面相邻。第一导电类型的第二漏区位于半导体本体中，并与第二体区，电介质区和上半导体表面相邻。两个漏极区彼此相邻。掩埋介质区域位于两个漏极区域的下方并且接触两个漏极区域的部分，从而（a）使第一漏极区域与第二体区域隔离，并且（b）将第二漏极区域与第一体区域隔离。可以根据在形成电介质区域之前或之后开始体区的形成的工艺来制造晶体管结构。

103. 发明授权

US5643809A Method for making high speed poly-emitter bipolar transistor 失效
标题翻译：制造高速多晶硅双极晶体管的方法
公开(公告)号：US5643809A
公开(公告)日：1997-07-01
申请号：US572449
申请日：1995-12-14
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H01L21/331 , H01L29/10 , H01L29/417 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/41708 , H01L29/732 , Y10S148/009 , Y10S148/01
摘要： Spacers are formed on the inside walls of a narrow silicon loss trench of a poly-emitter type bipolar transistor structure so that at most a narrow strip on the bottom of the trench receives high concentration doping when an extrinsic base region of the bipolar transistor is being doped. The narrowness of the exposed silicon surface which is etched to form the silicon loss trench slows vertical etching and thereby facilitates the formation of a shallow trench. The narrowness of the strip on the bottom of the trench which receives high concentration doping causes slow vertical diffusion of dopants. As a result, the highly doped link region which extends downward from the bottom of the trench does not extend downward much farther than the base region. A high cutoff frequency is therefore achievable by reducing the distance between the bottom of the base region and the top of the buried layer without decreasing the base-to-collector breakdown voltage.
摘要翻译：间隔物形成在多发射体型双极晶体管结构的窄硅损失沟槽的内壁上，使得当双极晶体管的非本征基极区为正时，沟槽底部的至少一个窄条接收高浓度掺杂掺杂。被蚀刻以形成硅损耗沟槽的暴露的硅表面的狭窄减慢了垂直蚀刻，从而有利于形成浅沟槽。接收高浓度掺杂的沟槽底部的条纹狭窄导致掺杂剂的慢垂直扩散。结果，从沟槽底部向下延伸的高度掺杂的链路区域不会比基极区域向下延伸得更远。因此，通过减小基极区域的底部和埋层的顶部之间的距离而不降低基极到集电极击穿电压，可以实现高截止频率。

104. 发明授权

US5574305A Walled-emitter transistor 失效
标题翻译：壁发射极晶体管
公开(公告)号：US5574305A
公开(公告)日：1996-11-12
申请号：US272277
申请日：1994-07-08
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L21/331 , H01L21/762 , H01L29/70
CPC分类号： H01L29/66272 , H01L21/76216 , Y10S148/01 , Y10S148/011 , Y10S148/102 , Y10S148/124
摘要： An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.
摘要翻译：本发明的实施例是具有硅衬底的半导体器件的工艺。该方法包括定位至少一个场注入掩模，并且在衬底中的双极有源区周围注入硅衬底，使得硼原子被阻挡在有源区之外，并且仅植入围绕所述有源区的场区，所述注入使得半导体器件的预定布局区域不需要增加以补偿BVbso问题。

105. 发明授权

US5479039A MOS electrostatic discharge protection device and structure 失效
标题翻译： MOS静电放电保护装置及结构
公开(公告)号：US5479039A
公开(公告)日：1995-12-26
申请号：US125967
申请日：1993-09-23
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H01L27/02 , H01L29/06 , H01L29/78
CPC分类号： H01L27/0251 , H01L27/0266
摘要： A PMOS transistor is coupled directly to both V.sub.CC and V.sub.SS, for use in an electrostatic discharge (ESD) protection device, thereby protecting the I/O pad(s) of an integrated circuit. The direct coupling of the PMOS transistor to both voltage levels, V.sub.CC and V.sub.SS, greatly reduces the overall ESD hazard, i.e, to all four ESD conditions: 1) positive against V.sub.SS, 2) negative against V.sub.SS, 3) positive against V.sub.CC, and 4) negative against V.sub.CC, the most critical of these tests being the positive against V.sub.SS and positive against V.sub.CC.
摘要翻译： PMOS晶体管直接耦合到VCC和VSS两者，用于静电放电（ESD）保护器件，从而保护集成电路的I / O焊盘。 PMOS晶体管与两个电压电平VCC和VSS的直接耦合大大降低了整体ESD危险，即所有四种ESD条件：1）对VSS为正，2）对VSS为负，3）为VCC为正，以及 4）对VCC负反馈，这些测试中最关键的是对VSS的正向和VCC的正向。

106. 发明授权

US5284800A Method for preventing the exposure of borophosphosilicate glass to the ambient and stopping phosphorus ions from infiltrating silicon in a semiconductor process 失效
标题翻译：防止半导体工艺中硼磷硅酸盐玻璃暴露于环境并阻止磷离子渗入硅的方法
公开(公告)号：US5284800A
公开(公告)日：1994-02-08
申请号：US838538
申请日：1992-02-19
申请人： Chuen-Der Lien , Daniel Liao , Jowei Dun
发明人： Chuen-Der Lien , Daniel Liao , Jowei Dun
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , Y10S148/133
摘要： An embodiment of the present invention is a semiconductor fabrication process that deposits an oxide layer after a step to make contact openings in a BPSG layer and before a contact reflow step. The oxide allows implant dopants to be properly activated in the contact reflow step without excessive reflow of the BPSG.
摘要翻译：本发明的一个实施方案是半导体制造方法，其在步骤之后沉积氧化物层以在BPSG层中和在接触回流步骤之前进行接触开口。氧化物允许在接触回流步骤中适当地激活注入掺杂剂，而不会使BPSG过度回流。

107. 发明授权

US5173627A Circuit for outputting a data signal following an output enable command signal 失效
标题翻译：用于在输出使能命令信号之后输出数据信号的电路
公开(公告)号：US5173627A
公开(公告)日：1992-12-22
申请号：US731502
申请日：1991-07-17
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： G11C7/10 , H03K17/16 , H03K19/0944 , H03K19/0948
CPC分类号： G11C7/1051 , H03K17/163 , H03K19/09441 , H03K19/0948
摘要： The invention provides an output enable control circuit with a three gate delay. The circuit includes a CMOS passgate or other transmission control and filtering means, one or more shunting transistors, and an output driver. The CMOS passgate, in conjunction with a first shunting transistor, allows an output enable command to control transmission of the data signal to the output driver. By properly tuning the CMOS passgate, bounce on the power supply and ground lines can be minimized. A second shunting transistor can be included to allow other data control signals, such as a write enable or chip select signal, to cease data output by the circuit. Additionally, a third shunting transistor, controlled by the data signal, can be included to allow fast turn off of the output driver.
摘要翻译：本发明提供具有三门延迟的输出使能控制电路。该电路包括CMOS通道或其他传输控制和滤波装置，一个或多个分流晶体管和输出驱动器。 CMOS通道与第一分流晶体管一起允许输出使能命令来控制数据信号传输到输出驱动器。通过适当调谐CMOS通道，可以使电源和接地线上的反弹最小化。可以包括第二分流晶体管以允许诸如写使能或片选信号的其它数据控制信号停止电路输出的数据。此外，可以包括由数据信号控制的第三分流晶体管，以允许输出驱动器的快速关断。

108. 发明授权

US07877657B1 Look-ahead built-in self tests 有权
标题翻译：先进的内置自检
公开(公告)号：US07877657B1
公开(公告)日：2011-01-25
申请号：US11960618
申请日：2007-12-19
申请人： Michael Miller , Chuen-Der Lien
发明人： Michael Miller , Chuen-Der Lien
IPC分类号： G01R31/3187 , G01R31/40
CPC分类号： G01R31/3016 , G01R31/318519
摘要： A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, performing a stress test of the functional element while the functional element is in the idle cycle, and indicating that the functional element, if it fails the stress test, is a potential future failing element. The stress test can include simultaneously providing a margining test voltage and a stress clock signal to the functional element. The stress test is performed in the background, during continuous operation of the integrated circuit device, such that normal operation of the integrated circuit device is not interrupted. Thereby, the method and apparatus of the present invention allows for failure prediction in a device before it happens, allowing for planned outages or workarounds and avoiding system downtime for unplanned repairs.
摘要翻译：公开了一种用于在操作期间预测集成电路的功能元件的故障的方法和装置。该方法包括：确定集成电路器件的功能元件是否处于空闲周期，在功能元件处于空闲周期内执行功能元件的应力测试，并且指示功能元件（如果其失效），是一个未来潜在的潜在因素。应力测试可以包括同时向功能元件提供裕度测试电压和应力时钟信号。在集成电路装置的连续运行期间，在背景中执行应力测试，使得集成电路装置的正常操作不被中断。因此，本发明的方法和装置允许在装置发生之前对装置进行故障预测，从而允许计划中断或解决方案，并避免计划外维修的系统停机时间。

109. 发明授权

US07414460B1 System and method for integrated circuit charge recycling 有权
标题翻译：集成电路充电回收系统及方法
公开(公告)号：US07414460B1
公开(公告)日：2008-08-19
申请号：US11395061
申请日：2006-03-31
申请人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Yeh
发明人： Chuen-Der Lien , Chau-Chin Wu , Tzong-Kwang Yeh
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： A charge recycling integrated circuit and a method for integrated circuit charge recycling. In one aspect, a charge storage collector is interposed between a high voltage supply or a low voltage supply and a function block of the integrated circuit. The charge collector is operable to selectively store a charge dissipated in the function block when the logic circuitry of the function block switches between a high voltage value and a low voltage value. The dissipated charge resulting from the switching in the logic circuitry of the function block is selectively stored to the charge collector and the charge collector selectively returns the charge stored on the charge collector to the high voltage supply, the low voltage supply or to another node in the integrated circuit as appropriate.
摘要翻译：电荷回收集成电路和集成电路充电回收方法。在一个方面，电荷存储收集器介于高压电源或低压电源和集成电路的功能块之间。当功能块的逻辑电路在高电压值和低电压值之间切换时，电荷收集器可操作以选择性地存储消耗在功能块中的电荷。由功能块的逻辑电路中的开关导致的耗散电荷被选择性地存储到电荷收集器中，并且电荷收集器选择性地将存储在电荷收集器上的电荷返回到高电压源，低电压电源或另一个节点集成电路适当。

110. 发明授权

US07248492B1 Method and apparatus for CAM with reduced cross-coupling interference 失效
公开(公告)号：US07248492B1
公开(公告)日：2007-07-24
申请号：US11393985
申请日：2006-03-30
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00 , G11C7/00
CPC分类号： G11C15/04 , G11C7/02
摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.

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