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101. 发明申请

US20060289909A1 Self-aligned low-k gate cap 失效
标题翻译：自对准低k门帽
公开(公告)号：US20060289909A1
公开(公告)日：2006-12-28
申请号：US11514605
申请日：2006-09-01
申请人： Oleg Gluschenkov , Jack Mandelman , Michael Belyansky , Bruce Doris
发明人： Oleg Gluschenkov , Jack Mandelman , Michael Belyansky , Bruce Doris
IPC分类号： H01L29/76
CPC分类号： H01L21/76834 , H01L21/28052 , H01L21/76897 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.
摘要翻译：提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。本发明的CMOS结构包括至少一个栅极区域，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。

102. 发明申请

US20060255375A1 ANTI-HALO COMPENSATION 有权
标题翻译：反哈马赔偿
公开(公告)号：US20060255375A1
公开(公告)日：2006-11-16
申请号：US10908442
申请日：2005-05-12
申请人： Omer Dokumaci , Oleg Gluschenkov
发明人： Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L31/112
CPC分类号： H01L29/105 , H01L21/26586 , H01L21/823412 , H01L29/6659 , H01L29/66636
摘要： An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting the compensating dopant at relatively high angle and high energy, the compensating dopant will pass into and through the gate region for short channels and have little or no impact on the total dopant concentration within the gate region. Where the channel is of a longer length, the high implant angle and the high implant energy cause the compensating dopant to lodge within the channel thereby neutralizing a portion of the dopant of the opposite type.
摘要翻译：提供了一种用于根据栅极长度控制半导体器件的有源区域中的净掺杂的装置和方法。选择补偿掺杂剂是一种掺杂剂，其将电中和衬底中相反类型的掺杂剂。通过以相对高的角度和高能量注入补偿掺杂剂，补偿掺杂剂将进入并通过用于短通道的栅极区域，并且对栅极区域内的总掺杂剂浓度几乎没有或没有影响。在通道长度较长的情况下，高注入角度和高注入能量使得补偿掺杂剂落入通道内，从而中和相反类型的掺杂剂的一部分。

103. 发明申请

US20060237803A1 ULTRA-THIN Hf-DOPED-SILICON OXYNITRIDE FILM FOR HIGH PERFORMANCE CMOS APPLICATIONS AND METHOD OF MANUFACTURE 有权
标题翻译：用于高性能CMOS应用的ULTRA-THIN Hf-DOPED-SILOON氧化膜和制造方法
公开(公告)号：US20060237803A1
公开(公告)日：2006-10-26
申请号：US10907935
申请日：2005-04-21
申请人： Wenjuan Zhu , Michael Chudzik , Oleg Gluschenkov , Dae-Gyu Park , Akihisa Sekiguchi
发明人： Wenjuan Zhu , Michael Chudzik , Oleg Gluschenkov , Dae-Gyu Park , Akihisa Sekiguchi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28097 , H01L21/28229 , H01L21/823857 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.
摘要翻译：一种半导体结构及其制造方法，包括在基极电介质层的顶部形成扩散控制稳定材料的均匀缓冲层，然后形成含有过渡金属原子源的均匀层，然后退火结构将过渡金属原子从其源极扩散通过扩散控制材料并进入基极栅极电介质层。

104. 发明申请

US20060125008A1 DUAL STRESSED SOI SUBSTRATES 有权
标题翻译：双应力SOI衬底
公开(公告)号：US20060125008A1
公开(公告)日：2006-06-15
申请号：US10905062
申请日：2004-12-14
申请人： Dureseti Chidambarrao , Bruce Doris , Oleg Gluschenkov , Omer Dokumaci , Huilong Zhu
发明人： Dureseti Chidambarrao , Bruce Doris , Oleg Gluschenkov , Omer Dokumaci , Huilong Zhu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

105. 发明申请

US20060118825A1 Nanocircuit and self-correcting etching method for fabricating same 审中-公开
标题翻译：纳米电路及其自校正蚀刻方法
公开(公告)号：US20060118825A1
公开(公告)日：2006-06-08
申请号：US11337398
申请日：2006-01-23
申请人： Omer Dokumaci , Oleg Gluschenkov
发明人： Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L29/06
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/82385 , Y10S438/947
摘要： A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively; the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.
摘要翻译：提供了用于制造微结构的自校正蚀刻（SCORE）工艺。本发明的SCORE方法对于降低硬掩模的预选特征而不降低每个晶片内的临界尺寸（CD）的变化特别有用。或者; 通过应用SCORE可以显着降低印刷过程中产生的硬掩模特征的CD变化。因此，可以可靠地制造超亚光刻特征（例如，纳米结构）。因此，本发明的方法可以用于提高电路性能，同时提高制造成品率。

106. 发明申请

US20060060925A1 SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS AND METHODS 有权
标题翻译：具有不同表面方向的活动区域的半导体器件结构和方法
公开(公告)号：US20060060925A1
公开(公告)日：2006-03-23
申请号：US10711416
申请日：2004-09-17
申请人： Bruce Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/045 , H01L21/76275 , H01L21/76278 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7842
摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.
摘要翻译：公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个其他。

107. 发明申请

US20060043421A1 MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE 有权
标题翻译：具有高K介质的通道顶表面的多栅极器件
公开(公告)号：US20060043421A1
公开(公告)日：2006-03-02
申请号：US10711200
申请日：2004-09-01
申请人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L27/10
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译：多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。保护层可以在蚀刻过程中保护高k电介质层。

108. 发明授权

US06982196B2 Oxidation method for altering a film structure and CMOS transistor structure formed therewith 失效
标题翻译：用于改变由其形成的膜结构和CMOS晶体管结构的氧化方法
公开(公告)号：US06982196B2
公开(公告)日：2006-01-03
申请号：US10605889
申请日：2003-11-04
申请人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Diane C. Boyd , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

109. 发明申请

US20050280099A1 TEMPERATURE STABLE METAL NITRIDE GATE ELECTRODE 有权
标题翻译：温度稳定的金属硝酸盐电极
公开(公告)号：US20050280099A1
公开(公告)日：2005-12-22
申请号：US10710063
申请日：2004-06-16
申请人： Dae-Gyu Park , Cyril Cabral , Oleg Gluschenkov , Hyungjun Kim
发明人： Dae-Gyu Park , Cyril Cabral , Oleg Gluschenkov , Hyungjun Kim
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.
摘要翻译：提供了一种集成电路，其包括形成在衬底上的FET栅极结构。该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。优选地，该层为W N x X，x为约0.9。改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。特别地，在WN 层中改变x允许调节不同FET中的阈值电压。多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

110. 发明申请

US20050202672A1 METHOD FOR MANUFACTURING TUNGSTEN/POLYSILICON WORD LINE STRUCTURE IN VERTICAL DRAM AND DEVICE MANUFACTURED THEREBY 失效
标题翻译：在垂直DRAM中制造TUNGSTEN / POLYSILICON WORD LINE结构的方法及其制造的器件
公开(公告)号：US20050202672A1
公开(公告)日：2005-09-15
申请号：US10708530
申请日：2004-03-10
申请人： Ramachandra Divakaruni , Oleg Gluschenkov , Oh-Jung Kwon , Rajeev Malik
发明人： Ramachandra Divakaruni , Oleg Gluschenkov , Oh-Jung Kwon , Rajeev Malik
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/44 , H01L21/8234 , H01L21/8242 , H01L23/52 , H01L27/088 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L27/10894 , H01L27/10861 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprised of at least one semiconductor memory array and logic circuits. The memory array includes electrically conductive word lines. The logic circuits include logic transistors with electrically conductive gates. The gates of the logic transistors and the word lines are composed of polysilicon and a metal layer. The metal layer is thicker than the polysilicon layer in the word lines; and the metal layer is thinner than the polysilicon layer in the gates of the logic transistors.
摘要翻译：一种由至少一个半导体存储器阵列和逻辑电路组成的集成电路。存储器阵列包括导电字线。逻辑电路包括具有导电栅极的逻辑晶体管。逻辑晶体管和字线的栅极由多晶硅和金属层组成。金属层比字线中的多晶硅层厚; 并且金属层比逻辑晶体管的栅极中的多晶硅层薄。

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