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1. 发明申请

US20050280099A1 TEMPERATURE STABLE METAL NITRIDE GATE ELECTRODE 有权
标题翻译：温度稳定的金属硝酸盐电极
公开(公告)号：US20050280099A1
公开(公告)日：2005-12-22
申请号：US10710063
申请日：2004-06-16
申请人： Dae-Gyu Park , Cyril Cabral , Oleg Gluschenkov , Hyungjun Kim
发明人： Dae-Gyu Park , Cyril Cabral , Oleg Gluschenkov , Hyungjun Kim
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.
摘要翻译：提供了一种集成电路，其包括形成在衬底上的FET栅极结构。该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。优选地，该层为W N x X，x为约0.9。改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。特别地，在WN 层中改变x允许调节不同FET中的阈值电压。多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

2. 发明申请

US20060040439A1 Temperature stable metal nitride gate electrode 有权
公开(公告)号：US20060040439A1
公开(公告)日：2006-02-23
申请号：US11203952
申请日：2005-08-15
申请人： Dae-Gyu Park , Cyril Cabral , Oleg Gluschenkov , Hyungjun Kim
发明人： Dae-Gyu Park , Cyril Cabral , Oleg Gluschenkov , Hyungjun Kim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

3. 发明申请

US20060001162A1 Nitride and polysilicon interface with titanium layer 审中-公开
标题翻译：氮化物和多晶硅界面与钛层
公开(公告)号：US20060001162A1
公开(公告)日：2006-01-05
申请号：US11084724
申请日：2005-03-18
申请人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
发明人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/28052 , H01L21/28061 , H01L21/76838 , H01L21/76855 , H01L21/823828 , H01L21/823842 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L2221/1078
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要翻译：提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34）并且在氮化钨层上形成钨层。该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

4. 发明申请

US20050087824A1 HIGH PERFORMANCE FET WITH LATERALLY THIN EXTENSION 失效
标题翻译：高性能FET，具有较小的延伸性
公开(公告)号：US20050087824A1
公开(公告)日：2005-04-28
申请号：US10605769
申请日：2003-10-24
申请人： Cyril Cabral , Omer Dokumaci , Oleg Gluschenkov
发明人： Cyril Cabral , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： G05F1/10 , G05F3/02 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/51 , H01L29/76 , H01L29/772 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28194 , H01L21/28202 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7836
摘要： field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.
摘要翻译：场效应晶体管（FET），包括FET的集成电路（IC）芯片和形成FET的方法。 FET在器件沟道上方具有器件沟道和栅极，在薄沟道的每个端部具有掺杂的源极/漏极延伸。低电阻材料层（例如硅化物层）的一部分设置在源极/漏极延伸部分上。掺杂延伸部分上的部分横向形成与掺杂源极/漏极延伸部的直接接触。栅极上的任何低电阻材料层与源极/漏极延伸部分上的低电阻材料部分分离。

5. 发明申请

US20050148142A1 High performance FET with laterally thin extension 失效
标题翻译：高性能FET，横向薄延伸
公开(公告)号：US20050148142A1
公开(公告)日：2005-07-07
申请号：US11074223
申请日：2005-03-07
申请人： Cyril Cabral , Omer Dokumaci , Oleg Gluschenkov
发明人： Cyril Cabral , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： G05F1/10 , G05F3/02 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/51 , H01L29/76 , H01L29/772 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28194 , H01L21/28202 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7836
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET在器件沟道上方具有器件沟道和栅极，在薄沟道的每个端部具有掺杂的源极/漏极延伸。低电阻材料层（例如硅化物层）的一部分设置在源极/漏极延伸部分上。掺杂延伸部分上的部分横向形成与掺杂源极/漏极延伸部的直接接触。栅极上的任何低电阻材料层与源极/漏极延伸部分上的低电阻材料部分分离。

6. 发明申请

US20050112857A1 ULTRA-THIN SILICIDATION-STOP EXTENSIONS IN MOSFET DEVICES 有权
公开(公告)号：US20050112857A1
公开(公告)日：2005-05-26
申请号：US10707175
申请日：2003-11-25
申请人： Oleg Gluschenkov , Cyril Cabral , Omer Dokumaci , Christian Lavoie
发明人： Oleg Gluschenkov , Cyril Cabral , Omer Dokumaci , Christian Lavoie
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/8234 , H01L27/092 , H01L29/08 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/28518 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide an the channel. On an appropriately prepared substrate, a selective etching process is performed to expose the sides of the channel region (transistor body). A very thin layer of a silicidation-stop material, e.g., SiGe, is disposed in the etched away area, coating the exposed sides of the channel region. The silicidation-stop material is doped (highly) appropriately for the type of MOSFET being formed (n-channel or p-channel). The etched away areas are then filled with silicon, e.g., by an Si epi process. Silicidation is then performed (to form, e.g., CoSi2) on the newly filled areas. The silicidation stop material constrains silicidation to the silicon fill material, but prevents silicide expansion past the silicidation stop material. Because the germanium (Ge) in SiGe is insoluble in CoSi2, the SiGe acts as a barrier to silicidation, permitting silicidation to go to completion in the Si fill but stopping silicidation at the SiGe boundary when silicidation is performed at a temperature above a silicidation threshold temperature for Si, but below a silicidation threshold temperature for SiGe. This results in a very compact, well-defined lateral junction characterized by a thin layer of SiGe disposed between silicide lateral extensions and the sides of the channel region. Because of the thin, highly-doped SiGe layer between the channel and the silicide lateral extensions, the extension resistance is very low.

7. 发明申请

US20060264048A1 Interconnect Structure Diffusion Barrier With High Nitrogen Content 有权
标题翻译：具有高氮含量的互连结构扩散屏障
公开(公告)号：US20060264048A1
公开(公告)日：2006-11-23
申请号：US11461220
申请日：2006-07-31
申请人： Cyril Cabral , Steffen Kaldor , Hyungjun Kim , Stephen Rossnagel
发明人： Cyril Cabral , Steffen Kaldor , Hyungjun Kim , Stephen Rossnagel
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.
摘要翻译：在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。

8. 发明申请

US20050110144A1 Interconnect Structure Diffusion Barrier with High Nitrogen Content 有权
标题翻译：具有高氮含量的互连结构扩散屏障
公开(公告)号：US20050110144A1
公开(公告)日：2005-05-26
申请号：US10707117
申请日：2003-11-21
申请人： Cyril Cabral , Steffen Kaldor , Hyungjun Kim , Stephen Rossnagel
发明人： Cyril Cabral , Steffen Kaldor , Hyungjun Kim , Stephen Rossnagel
IPC分类号： H01L21/768 , H01L23/48 , H01L23/532
CPC分类号： H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.
摘要翻译：在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。

9. 发明申请

US20060003557A1 Atomic layer deposition metallic contacts, gates and diffusion barriers 有权
标题翻译：原子层沉积金属触点，栅极和扩散屏障
公开(公告)号：US20060003557A1
公开(公告)日：2006-01-05
申请号：US11214211
申请日：2005-08-29
申请人： Cyril Cabral , Hyungjun Kim , Stephen Rossnagel
发明人： Cyril Cabral , Hyungjun Kim , Stephen Rossnagel
IPC分类号： H01L21/20 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/28088 , H01L21/28562 , H01L21/32053 , H01L21/76841 , H01L29/4966 , H01L2221/1078
摘要： The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.
摘要翻译：本发明通过利用原子层沉积（ALD）提供含有IVB族或VB族金属，硅和任选的氮的金属膜。特别地，本发明提供形成金属硅化物的低温热ALD方法和形成金属氮化硅膜的等离子体增强原子层沉积（PE-ALD）方法。本发明的方法能够在基材的表面上形成厚度为单层或更薄的金属膜。本发明中提供的金属膜可用于接触金属化，金属栅极或扩散阻挡层。

10. 发明申请

US20050042865A1 Atomic layer deposition of metallic contacts, gates and diffusion barriers 有权
公开(公告)号：US20050042865A1
公开(公告)日：2005-02-24
申请号：US10643534
申请日：2003-08-19
申请人： Cyril Cabral , Hyungjun Kim , Stephen Rossnagel
发明人： Cyril Cabral , Hyungjun Kim , Stephen Rossnagel
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L29/49 , H01L21/425 , H01L21/44
CPC分类号： H01L21/28088 , H01L21/28562 , H01L21/32053 , H01L21/76841 , H01L29/4966 , H01L2221/1078
摘要： The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.

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