专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

101. 发明申请

US20060114711A1 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US20060114711A1
公开(公告)日：2006-06-01
申请号：US11001870
申请日：2004-12-01
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Gunjan Pandya , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Gunjan Pandya , Vivek De
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
摘要翻译：在一个实施例中，提供了包括一个或多个列的存储器阵列，每个列包括被分成位单元组的多个位单元，每组比特单元可控制地耦合到单独的位线。

102. 发明申请

US20060091935A1 Processor apparatus with body bias circuitry to delay thermal throttling 有权
标题翻译：具有主体偏置电路的处理器设备，用于延迟热调节
公开(公告)号：US20060091935A1
公开(公告)日：2006-05-04
申请号：US10982266
申请日：2004-11-03
申请人： James Tschanz , Stephen Tang , Siva Narendra , Vivek De
发明人： James Tschanz , Stephen Tang , Siva Narendra , Vivek De
IPC分类号： H03K3/01
CPC分类号： G06F1/206
摘要： Apparatuses and methods for delaying thermal throttling of processor devices by decreasing threshold voltages are disclosed.
摘要翻译：公开了通过降低阈值电压来延迟处理器装置的热节流的装置和方法。

103. 发明申请

US20060061400A1 Gating for dual edge-triggered clocking 失效
公开(公告)号：US20060061400A1
公开(公告)日：2006-03-23
申请号：US10947869
申请日：2004-09-23
申请人： James Tschanz , Dinesh Somasekhar , Vivek De
发明人： James Tschanz , Dinesh Somasekhar , Vivek De
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： Some embodiments provide reception of a clock signal, reception of a gating signal, and output of a gated clock signal to a dual edge-triggered-clocked circuit. The gated clock signal is based on the clock signal and on the gating signal.

104. 发明申请

US20060061382A1 Majority voter apparatus, systems, and methods 失效
标题翻译：多数选民设备，制度和方法
公开(公告)号：US20060061382A1
公开(公告)日：2006-03-23
申请号：US10947765
申请日：2004-09-23
申请人： Yibin Ye , James Tschanz , Muhammad Khellah , Vivek De
发明人： Yibin Ye , James Tschanz , Muhammad Khellah , Vivek De
IPC分类号： H03K19/003
CPC分类号： H03K19/23
摘要： Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.
摘要翻译：装置和系统以及方法和物品可以使用耦合到第一多个位输入和第二多个位输入的读出放大器来提供多数选举指示。

105. 发明申请

US20050226032A1 SRAM device having forward body bias control 有权
标题翻译：具有前向偏置控制的SRAM器件
公开(公告)号：US20050226032A1
公开(公告)日：2005-10-13
申请号：US10812894
申请日：2004-03-31
申请人： Stephen Tang , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz
发明人： Stephen Tang , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
摘要翻译：提供具有多个存储单元的SRAM器件。每个存储单元可以包括以交叉耦合的反相器配置耦合的多个晶体管。 NMOS晶体管可以以交叉耦合的反相器配置耦合到两个PMOS晶体管的主体，以便向交叉耦合的反相器配置的PMOS晶体管施加正向偏置。功率控制单元可以控制每个PMOS晶体管的电源电压，并且基于存储器单元的STANDBY模式将开关信号施加到NMOS晶体管。

106. 发明申请

US20050139999A1 Method and apparatus for applying body bias to integrated circuit die 失效
标题翻译：将体偏置施加到集成电路管芯的方法和装置
公开(公告)号：US20050139999A1
公开(公告)日：2005-06-30
申请号：US10747805
申请日：2003-12-29
申请人： Siva Narendra , James Tschanz , Victor Zia , Badarinath Kommandur , Vivek De
发明人： Siva Narendra , James Tschanz , Victor Zia , Badarinath Kommandur , Vivek De
IPC分类号： H01L21/60 , H01L23/34 , H01L23/367 , H01L23/50
CPC分类号： H01L23/367 , H01L23/50 , H01L24/31 , H01L24/75 , H01L24/81 , H01L24/83 , H01L2224/16225 , H01L2224/73253 , H01L2224/75 , H01L2224/81801 , H01L2224/83801 , H01L2924/01005 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152
摘要： In some embodiments, a method includes providing an integrated circuit (IC) die in a package. The IC die may have a metal layer on a back surface of the IC die. The method may also include applying a bias signal to the IC die via the metal layer.
摘要翻译：在一些实施例中，一种方法包括在封装中提供集成电路（IC）裸片。 IC芯片可以在IC芯片的背面上具有金属层。该方法还可以包括经由金属层向IC管芯施加偏置信号。

107. 发明授权

US5986473A Differential, mixed swing, tristate driver circuit for high performance and low power on-chip interconnects 失效
标题翻译：差分，混合摆幅，三态驱动电路，用于高性能和低功耗片上互连
公开(公告)号：US5986473A
公开(公告)日：1999-11-16
申请号：US1449
申请日：1997-12-31
申请人： Ram Kumar Krishnamurthy , Vivek De , Krishnamurthy Soumyanath
发明人： Ram Kumar Krishnamurthy , Vivek De , Krishnamurthy Soumyanath
IPC分类号： H03K19/0175 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/01707 , H03K19/018521
摘要： A driver to provide low voltage swings on a bus with fast switching times, the driver comprising two pairs of pullup and pulldown nMOSFETs, each pair operated in complementary fashion to each other, each pair with a high voltage rail at a smaller voltage than the data input logic HIGH voltage, and where each substrate of the nMOSFETs are biased so as to reduce their threshold voltages.
摘要翻译：驱动器在总线上提供低电压摆幅，具有快速的开关时间，驱动器包括两对上拉和下拉nMOSFET，每对互为互补的方式互相连接，每对具有电压低于数据的高压轨输入逻辑高电压，并且其中nMOSFET的每个衬底被偏置以便降低它们的阈值电压。

108. 发明授权

US08769376B2 Memory cell supply voltage control based on error detection 有权
公开(公告)号：US08769376B2
公开(公告)日：2014-07-01
申请号：US13626435
申请日：2012-09-25
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

109. 发明授权

US08301970B2 Sequential circuit with error detection 有权
标题翻译：具有错误检测的顺序电路
公开(公告)号：US08301970B2
公开(公告)日：2012-10-30
申请号：US12286067
申请日：2008-09-26
申请人： Keith Bowman , James Tachanz , Nam Sung Kim , Janice Lee , Chris Wilkerson , Shih-Lien L. Lu , Tanay Karnlk , Vivek De
发明人： Keith Bowman , James Tachanz , Nam Sung Kim , Janice Lee , Chris Wilkerson , Shih-Lien L. Lu , Tanay Karnlk , Vivek De
IPC分类号： H03M13/33 , H03M13/01
CPC分类号： H03K3/0375
摘要： Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
摘要翻译：提供了具有错误检测的顺序电路。例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。

110. 发明申请

US20100181607A1 INCREASING THE SURFACE AREA OF A MEMORY CELL CAPACITOR 有权
标题翻译：增加记忆体电容器的表面积
公开(公告)号：US20100181607A1
公开(公告)日：2010-07-22
申请号：US12749389
申请日：2010-03-29
申请人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号： H01L27/06
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译：描述了增加存储单元电容器的表面积的方法和装置。形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。衬底具有翅片。第一绝缘层沉积在邻近鳍片的衬底上。第二绝缘层上的开口形成在鳍上。第一导电层沉积在第二绝缘层和鳍上。第三绝缘层沉积在第一导电层上。第二导电层沉积在第三绝缘层上。第二导电层填充开口。第二导电层是提供与上金属层的互连。从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式