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    • 102. 发明申请
    • CHARGE PUMP CIRCUIT AND CHARGE PUMPING METHOD THEREOF
    • 充电泵电路及其充电泵送方法
    • US20090039948A1
    • 2009-02-12
    • US12187292
    • 2008-08-06
    • JUNG HWAN PARKIN-CHUL JEONG
    • JUNG HWAN PARKIN-CHUL JEONG
    • G05F3/02
    • H02M3/073
    • A charge pump circuit includes first and second charge pumps and a detector. The first charge pump outputs a first charge pump signal of an intermediate voltage level by performing a charge pumping operation in response to a command signal. The detector outputs a detection signal in response to the command signal when a voltage level of an output node is lower than a designated voltage voltage. The second charge pump charge-pumps the voltage level of the output node to a target charge-pumped voltage level higher than the intermediate voltage level and the designated voltage in response to the detection signal and the first charge pump signal.
    • 电荷泵电路包括第一和第二电荷泵和检测器。 第一电荷泵通过响应于命令信号执行电荷泵送操作来输出中间电压电平的第一电荷泵浦信号。 当输出节点的电压电平低于指定电压时,检测器响应于指令信号输出检测信号。 第二电荷泵充电 - 响应于检测信号和第一电荷泵信号,将输出节点的电压电平泵送到高于中间电压电平和指定电压的目标电荷泵送电压电平。
    • 103. 发明申请
    • Memory core and semiconductor memory device having the same
    • 存储器芯和半导体存储器件具有相同的功能
    • US20090034315A1
    • 2009-02-05
    • US12220422
    • 2008-07-24
    • Je-Min YuIn-Chul Jeong
    • Je-Min YuIn-Chul Jeong
    • G11C5/02G11C7/00G11C8/08
    • G11C11/4085G11C8/08G11C8/14
    • A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device.
    • 公开了一种能够减小芯连接区域面积的记忆体。 存储器芯包括第一副字线驱动电路和第一副字线控制信号发生电路。 第一子字线驱动电路设置在第一区域中,并产生第一字线驱动信号,以将第一字线驱动信号提供给阵列单元。 第一副字线控制信号发生电路设置在第一区域中,并且基于子字线驱动信号产生第一副字线控制信号。 因此,存储器芯具有小的尺寸,因此半导体器件也是如此。
    • 104. 发明授权
    • Variable reference level input circuit and method
    • 可变参考电平输入电路和方法
    • US07471108B2
    • 2008-12-30
    • US11298201
    • 2005-12-08
    • In-Chul Jeong
    • In-Chul Jeong
    • H03K19/0175H03K19/003
    • H03K5/082H03K5/003
    • We describe an input circuit and method. The input circuit includes a variable reference level generator that increases a level of a reference signal in proportion to a time when an input signal transits from a low level to a high level and decreases the level of the reference signal in proportion to a time when the input signal transits from a high level to a low level. An analyzer compares the level of the input signal with the level of the reference signal, determines the level of the input signal, and outputs a signal based on the comparison. The input circuit and method widen the minimum difference between the input and reference signal to facilitate analysis of the input signal.
    • 我们描述一种输入电路和方法。 输入电路包括可变参考电平发生器,其与输入信号从低电平转换到高电平的时间成比例地增加参考信号的电平,并且与参考信号的电平成比例地降低参考信号的电平 输入信号从高电平转换到低电平。 分析仪将输入信号的电平与参考信号的电平进行比较,确定输入信号的电平,并根据比较输出信号。 输入电路和方法扩大了输入和参考信号之间的最小差异,便于分析输入信号。
    • 105. 发明申请
    • MEMORY DEVICES AND SYSTEMS INCLUDING ERROR-CORRECTION CODING AND METHODS FOR ERROR-CORRECTION CODING
    • 包含错误修正编码的存储器件和系统以及用于错误校正编码的方法
    • US20080307285A1
    • 2008-12-11
    • US12132754
    • 2008-06-04
    • Kyung-hyun KIMKwang-il PARKIn-chul JEONG
    • Kyung-hyun KIMKwang-il PARKIn-chul JEONG
    • H03M13/03G06F11/08
    • H04L1/0042
    • In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer.
    • 一方面,存储器件包括存储单元阵列,将内部数据传送到存储单元阵列和从存储单元阵列发送内部数据的并行内部数据路径,发送和接收外部数据的数据驱动器以及延迟和传送外部数据的数据缓冲器 由数据驱动器接收到内部数据路径,并且延迟并将从存储单元阵列发送的内部数据传送到数据驱动器。 存储装置还包括纠错码发生器,该纠错码产生器基于在内部数据路径上发送的内部数据产生纠错码(EC),延迟由纠错码发生器产生的纠错码的EC缓冲器,EC 发送由EC缓冲器延迟的纠错码的驱动器,以及可变地控制数据缓冲器和EC缓冲器中的至少一个的延迟时间的等待时间控制器。