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91. 发明授权

US06204689B1 Input/output interconnect circuit for FPGAs 有权
标题翻译： FPGA的输入/输出互连电路
公开(公告)号：US06204689B1
公开(公告)日：2001-03-20
申请号：US09321513
申请日：1999-05-27
申请人： Andrew K. Percey , Trevor J. Bauer , Steven P. Young
发明人： Andrew K. Percey , Trevor J. Bauer , Steven P. Young
IPC分类号： H01L2500
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： An input/output interconnect (IOI) circuit is provided for coupling input/output (IO) blocks to an array of configurable logic tiles in a field programmable gate array (FPGA). Each of the tiles includes a configurable logic block and a programmable interconnect structure that includes a plurality of intermediate-length buses. The intermediate-length buses are staggered, such that only a subset of the intermediate-length buses routed by a logic block is connected to the logic block. The IOI circuit includes routing circuits at the perimeter of the array for terminating the intermediate-length buses. In one embodiment, the routing circuits connect various ends of unidirectional intermediate-length buses in a U-turn configuration, thereby making use of all of the intermediate-length buses, and maintaining a regular pattern of intermediate-length buses in the tiles. In another embodiment, various ends of bi-directional intermediate-length buses are terminated to long lines through programmable interconnection points (PIPs). In another embodiment, PIPs are provided to enable horizontal long lines to be connected to horizontal intermediate-length buses, which in turn, can be connected to vertical long lines, thereby providing a low-skew, high fanout routing network.
摘要翻译：提供输入/输出互连（IOI）电路用于将输入/输出（IO）块耦合到现场可编程门阵列（FPGA）中的可配置逻辑块阵列。每个瓦片包括可配置逻辑块和包括多个中长度总线的可编程互连结构。中间长度总线是交错的，使得只有由逻辑块路由的中间长度总线的子集连接到逻辑块。 IOI电路包括用于终止中长度总线的阵列周边的路由电路。在一个实施例中，路由电路将单向中长度总线的各端连接在U形结构中，从而利用所有的中长度总线，并在瓦片中保持中长度总线的规则图案。在另一个实施例中，双向中间长度总线的各个端点通过可编程互连点（PIP）终止于长行。在另一个实施例中，提供PIP以使得水平长线能够连接到水平中间长度总线，其又可以连接到垂直长线，从而提供低偏移，高扇出路由网络。

92. 发明授权

US06201410B1 Wide logic gate implemented in an FPGA configurable logic element 有权
标题翻译：宽逻辑门在FPGA可配置逻辑元件中实现
公开(公告)号：US06201410B1
公开(公告)日：2001-03-13
申请号：US09374470
申请日：1999-08-13
申请人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/1778
摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.
摘要翻译：本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

93. 发明授权

US06177627B1 Solar cell array with multiple rows of cells and collapsible reflectors 有权
标题翻译：具有多排电池和可折叠反射器的太阳能电池阵列
公开(公告)号：US06177627B1
公开(公告)日：2001-01-23
申请号：US09337624
申请日：1999-06-21
申请人： Dave Murphy , Michael I. Eskenazi , Brian R. Spence
发明人： Dave Murphy , Michael I. Eskenazi , Brian R. Spence
IPC分类号： H01L2500
CPC分类号： H01L31/0547 , B64G1/222 , B64G1/443 , F24S20/50 , F24S23/70 , H02S30/20 , Y02E10/40 , Y02E10/52 , Y10S136/292
摘要： An improved solar panel for a spacecraft. The solar panel has a rigid base, at least one row of solar cells, and at least one elongated, collapsible, self-deploying reflector. Preferably, a plurality of rows and the reflectors are mounted on the face of the base and are generally parallel to each other in an alternating fashion. The deployed reflector forms a triangular shape having a first and second reflecting side that reflects radiation onto adjacent rows of solar cells. The collapsible reflector has a reflector sheet and an erector that deploys the sheet to form the triangular shape. The sheet is mounted to the base along its two lengthwise edges. The erector is mounted to the base beneath the sheet and adjacent to one of the sheet's lengthwise edges. The erector has a rigid erector arm that tilts upwardly to engage the underside of the sheet and to deploy the sheet into the triangular shape. The deployed triangular shape comprises a first and second reflecting side that reflects incident radiation onto adjacent rows of solar cells. Preferably, the first and second reflecting sides of the reflector are substantially symmetrically disposed about the longitudinal bisecting plane of the reflector when the reflector is in a deployed position.
摘要翻译：一种用于航天器的改进的太阳能电池板。太阳能电池板具有刚性基座，至少一排太阳能电池，以及至少一个细长的，可折叠的自展开反射器。优选地，多个行和反射器安装在基座的表面上并且以交替的方式大致彼此平行。部署的反射器形成具有将辐射反射到相邻行太阳能电池上的第一和第二反射侧的三角形形状。可折叠的反射器具有反射片和竖立件，以形成三角形形状。片材沿其两个纵向边缘安装到基座上。竖立装置安装在片材下面的基部上并且邻近片材的纵向边缘之一。竖立器具有一个刚性竖立臂，它向上倾斜以接合片材的下侧并将片材展开成三角形形状。部署的三角形形状包括将入射辐射反射到相邻行太阳能电池上的第一和第二反射侧。优选地，当反射器处于展开位置时，反射器的第一和第二反射侧基本上对称地设置在反射器的纵向平分平面周围。

94. 发明授权

US06801052B2 Field programmable gate array core cell with efficient logic packing 失效
标题翻译：现场可编程门阵列核心单元，具有高效的逻辑封装
公开(公告)号：US06801052B2
公开(公告)日：2004-10-05
申请号：US10269830
申请日：2002-10-11
申请人： Daniel J. Pugh , Andrew W. Fox , Dale Wong
发明人： Daniel J. Pugh , Andrew W. Fox , Dale Wong
IPC分类号： H01L2500
CPC分类号： G06F17/5054
摘要： A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.
摘要翻译：具有一个或多个查找表（LUT）和可选逻辑门的现场可编程门阵列（FPGA）核心单元被呈现为传统的基于LUT的FPGA核心单元的空间有效的替代。基于LUT的FPGA核心单元的基于熟悉FlowMap算法的算法实现了布尔逻辑网络映射到所公开的FPGA核心单元中。

95. 发明授权

US06800801B2 Photovoltaic power generating structure 失效
标题翻译：光伏发电结构
公开(公告)号：US06800801B2
公开(公告)日：2004-10-05
申请号：US09315018
申请日：1999-05-20
申请人： Makoto Sasaoka , Yuji Inoue , Satoru Shiomi , Hidehisa Makita
发明人： Makoto Sasaoka , Yuji Inoue , Satoru Shiomi , Hidehisa Makita
IPC分类号： H01L2500
CPC分类号： H02S20/23 , H01L31/048 , H01L31/0504 , H02S40/36 , Y02B10/12 , Y02B10/20 , Y02E10/50
摘要： There is disclosed a photovoltaic power generating structure in which a solar cell module is arranged on a base member, wherein a closed space portion cut off from the air is provided between the base member and the solar cell module. Thus, there can be provided a photovoltaic power generating structure which can be easily constructed at a low installation cost, can maintain a good output as a photovoltaic power generating system, is excellent in environmental resistance, and can improve fireproofness.
摘要翻译：公开了一种光伏发电结构，其中太阳能电池模块设置在基座部件上，其中在空气中切断的封闭空间部分设置在基座部件和太阳能电池模块之间。因此，可以提供一种能够以低安装成本容易地构造的光伏发电结构，能够作为光伏发电系统保持良好的输出，耐环境性优异，能够提高耐火性。

96. 发明授权

US06794904B2 Semiconductor integrated circuit device including logic gate that attains reduction of power consumption and high-speed operation 失效
标题翻译：包括逻辑门的半导体集成电路器件，其降低功耗和高速操作
公开(公告)号：US06794904B2
公开(公告)日：2004-09-21
申请号：US10281951
申请日：2002-10-29
申请人： Tsukasa Ooishi , Masatoshi Ishikawa
发明人： Tsukasa Ooishi , Masatoshi Ishikawa
IPC分类号： H01L2500
CPC分类号： G11C5/147 , H03K19/0016
摘要： A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.
摘要翻译：半导体集成电路器件具有用于逻辑电路的分层供电系统。逆变器具有来自主电源线和较高电位的副电源线以及较低电位的主地线和次地线的电源。放置内部电源降压转换器以将主电源线的电压设置为高于较高电位的正常工作电压。放置内部电源升压电路，将主接地线的电压设定为低于较低电位的正常工作电压。当各个电源线由开关晶体管短路时，每个电源线的电压可以保持在操作电源电压。

97. 发明授权

US06791355B2 Spare cell architecture for fixing design errors in manufactured integrated circuits 失效
公开(公告)号：US06791355B2
公开(公告)日：2004-09-14
申请号：US10352470
申请日：2003-01-27
申请人： Alain Vergnes
发明人： Alain Vergnes
IPC分类号： H01L2500
CPC分类号： H03K19/17764 , H03K19/1774 , H03K19/17796
摘要： A fully self-sufficient configurable spare gate cell that has two types of inputs: a functional input bus and an equation input bus, whereby the spare gate cell can be transformed into any sum of product operator by the assertion of certain signals to the equation input bus. In a spare state, the functional input buses are connected to an area of pre-defined logic where the need for bug fixes are high. Thus, the spare cell would be automatically placed close to the bug-fix area during the place-and-route phase of chip design, thereby reducing the need to look for routing channels.

98. 发明授权

US06741122B2 Routing technique to adjust clock skew using frames and prongs 有权
标题翻译：使用帧和分支调整时钟偏移的路由技术
公开(公告)号：US06741122B2
公开(公告)日：2004-05-25
申请号：US09758603
申请日：2001-01-12
申请人： Ashok K. Kapoor , Lei Lin
发明人： Ashok K. Kapoor , Lei Lin
IPC分类号： H01L2500
CPC分类号： H05K1/0248 , G06F1/10 , H03K5/14 , H05K1/0219 , H05K2201/09236 , H05K2201/09263 , H05K2201/09781
摘要： An improved method and design for adjusting clock skew in a wire trace is disclosed. Aspects of the invention include a corrugated pattern wire trace bracketed by a pair of parallel conducting wire frames with wire extensions projecting between the corrugations of the wire trace. The wire frames are connected to a voltage supply. The transmission properties of the wire trace, and thus the degree of clock skew associated with the wire trace, are affected by the number of wire extensions protruding between the corrugations, their degree of penetration, as well as other factors inherent in the design. The present design can achieve the same degree of clock skew with a smaller surface area covered and with fewer resistive losses than with prior art designs.
摘要翻译：公开了一种用于调整线迹中的时钟偏移的改进方法和设计。本发明的方面包括由一对平行的导线框架包围的波纹状图案线迹线，其中导线延伸部突出在线迹的波纹之间。线框连接到电源。导线轨迹的传输特性以及因此与线迹相关联的时钟偏移程度受到波纹之间突出的导线延伸的数量，它们的穿透程度以及设计中固有的其它因素的影响。与现有技术的设计相比，本设计可以实现相同程度的时钟偏移，具有较小的表面积并且具有较少的电阻损耗。

99. 发明授权

US06703895B1 Semiconductor component and method of operating same 有权
标题翻译：半导体元件及其操作方法
公开(公告)号：US06703895B1
公开(公告)日：2004-03-09
申请号：US10256820
申请日：2002-09-26
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2500
CPC分类号： H01L29/7816 , H01L29/4238 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of a method of redistributing power in a semiconductor component includes varying a saturation current between a drain terminal (330) and a source terminal (320) of a field effect transistor (FET) (200, 500). The FET is at least a portion of the semiconductor component. The threshold voltage of the FET is maintained substantially constant across the FET while the drain-to-source saturation current per unit area is varied across the FET. In one embodiment, the drain-to-source saturation current per unit area is varied such that it is lower at a center of the FET than at a periphery of the FET. In particular embodiments, the drain-to-source saturation current per unit area may be varied across the FET by changing one or more of the gate-to-source voltage, the channel length, the channel width, the gate oxide thickness, and the channel mobility across the FET.
摘要翻译：在半导体部件中重新分配功率的方法的实施例包括改变场效应晶体管（FET）（200,500）的漏极端子（330）和源极端子（320）之间的饱和电流。 FET是半导体部件的至少一部分。 FET的阈值电压在整个FET上保持基本恒定，同时跨FET的每单位面积的漏极 - 源极饱和电流是变化的。在一个实施例中，每单位面积的漏极 - 源极饱和电流是变化的，使得其在FET的中心处比在FET的周边处更低。在特定实施例中，通过改变栅极 - 源极电压，沟道长度，沟道宽度，栅极氧化物厚度和栅极 - 源极电压之间的一个或多个，可以跨FET跨越每单位面积的漏极 - 源极饱和电流 FET上的通道迁移率。

100. 发明授权

US06677781B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06677781B2
公开(公告)日：2004-01-13
申请号：US10170369
申请日：2002-06-14
申请人： Yasuyuki Ishikawa , Kouji Ichikawa , Hideaki Ishihara
发明人： Yasuyuki Ishikawa , Kouji Ichikawa , Hideaki Ishihara
IPC分类号： H01L2500
CPC分类号： H01L24/06 , H01L23/50 , H01L23/5286 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01004 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , Y10T307/50 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A common power source line has first power supply points and second power supply points. The first power supply points are provided for supplying electric power to buffer circuits of low-frequency signal pads, while the second power supply points are provided for buffer circuits of high-frequency signal pads. A wiring distance from a power source pad to the second power supply points as well as a wiring distance from the first power supply points to the second power supply points are set to be relatively long in an overall wiring arrangement on a chip.
摘要翻译：公共电源线具有第一电源点和第二电源点。第一电源点被提供用于向低频信号焊盘的缓冲电路供电，而第二电源点被提供给高频信号焊盘的缓冲电路。在芯片上的整体布线布置中，从电源焊盘到第二电源点的布线距离以及从第一电源点到第二电源点的布线距离被设置为相对较长。

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