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91. 发明申请

US20010054735A1 Non-volatile semiconductor storage apparatus and manufacturing method thereof 失效
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US20010054735A1
公开(公告)日：2001-12-27
申请号：US09837734
申请日：2001-04-17
发明人： Takaaki Nagai
IPC分类号： H01L029/94 , H01L029/76 , H01L021/82 , H01L031/062 , H01L029/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A memory cell array is provided at a non-volatile semiconductor storage apparatus. In a memory cell array, the unit cell includes a memory cell field effect transistor and a select field effect transistor. The memory cell field effect transistor has a floating gate and a control gate. The select field effect transistor has a drain connected to a source of the memory cell field effect transistor. The floating gate and control gate extends to a position above a gate of the select field effect transistor.
摘要翻译：存储单元阵列设置在非易失性半导体存储装置中。在存储单元阵列中，单位单元包括存储单元场效应晶体管和选择场效应晶体管。存储单元场效应晶体管具有浮栅和控制栅。选择场效应晶体管具有连接到存储单元场效应晶体管的源极的漏极。浮动栅极和控制栅极延伸到选择场效应晶体管的栅极上方的位置。

92. 发明申请

US20010050407A1 Anti-fuse structure and method of writing and reading in integrated circuits 有权
标题翻译：集成电路中的反熔丝结构和写入和读取方法
公开(公告)号：US20010050407A1
公开(公告)日：2001-12-13
申请号：US09873035
申请日：2001-06-02
发明人： Tito Gelsomini , Kemal Tamer San
IPC分类号： H01L021/82 , H01L021/326 , H01L021/479 , H01L029/00
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.
摘要翻译：嵌入在集成电路（IC）中的信息写入寄存器由形成在嵌套在n阱中的隔离p阱中的多个可独立寻址的门控元件构成。位于p阱上的栅极位于几何形状上的绝缘体上，使得其在施加过应力电压脉冲时局部易于导电，由此二进制信息可以被永久地编码到写寄存器中。过应力电压脉冲施加在栅极和p阱之间，并且当具有相反极性和较短持续时间的p阱脉冲叠加预定极性和持续时间的写使能脉冲时产生。

93. 发明申请

US20010036688A1 Method for design and manufacture of semiconductors 有权
标题翻译：半导体设计和制造方法
公开(公告)号：US20010036688A1
公开(公告)日：2001-11-01
申请号：US09829939
申请日：2001-04-11
发明人： Zvi Or-Bach
IPC分类号： H01L021/82
CPC分类号： G06F17/5045 , G06F2217/04 , G06F2217/66 , G06F2217/68
摘要： This invention discloses a method for designing and manufacturing semiconductors including the steps of: (i) producing a fab-ready design for a semiconductor device by importing into the design at least one core from a remote source, the core bearing an identification indicium, (ii) utilizing the fab-ready design to fabricate the semiconductor device, and (iii) reading the identification indicium from the semiconductor device to indicate incorporation of the at least one core therein.
摘要翻译：本发明公开了一种半导体设计和制造方法，包括以下步骤：（i）通过从远程源导入至少一个核心，产生具有识别标记的核心（半导体器件） ii）利用制造厂准备的设计来制造半导体器件，以及（iii）从半导体器件读取识别标记，以指示其中的至少一个核心的结合。

94. 发明申请

US20010034084A1 METHOD FOR MAKING A PEDESTAL FUSE 失效
标题翻译：制作保险丝的方法
公开(公告)号：US20010034084A1
公开(公告)日：2001-10-25
申请号：US09844125
申请日：2001-04-26
申请人： International Business Machines Corporation
发明人： Dennis P. Bouldin , Timothy H. Daubenspeck , William T. Motsiff
IPC分类号： H01L021/82
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially- similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of nulleasy to laser deletenull thin metal fuses within segments of thick metal lines. This applies to wiring layers formed from nullhighnull melting temperature metals and those defined using a damascene process. For example, copper back end of line (Cu BEOL) damascene wiring, as used with CMOS can use the invention. The technique achieves high yield fusing for technologies that use thick wiring layers. The structure separates the thickness of the fuse segment from the remainder of the wiring line. The structure can be used with very thick, e.g., >1.2null wiring and very thin, e.g.,
摘要翻译：公开了一种制造金属化熔丝线的结构和方法。该结构可以形成在半导体衬底上，包括形成在衬底上的绝缘体结构，绝缘体结构具有上层和下层，上部比下部薄，绝缘结构具有多个不同深度的开口以及镶嵌在绝缘体结构中的金属结构，具有第一和第二部分的金属结构和在其之间的第三部分基本上比第一和第二部分更具有阻力，第三部分的厚度基本上类似于绝缘体结构的上层。上层包括氮化物，下层包括氧化物，金属结构包括铜。熔丝结构允许在厚金属线段内形成“易于激光删除”的薄金属保险丝。这适用于由“高”熔融金属形成的布线层和使用镶嵌工艺定义的布线层。例如，与CMOS一起使用的铜后端（Cu BEOL）镶嵌布线可以使用本发明。该技术实现了使用厚布线层的技术的高产率熔合。该结构将熔丝段的厚度与布线的其余部分分开。该结构可以使用非常厚的例如>1.2μm的布线和非常薄的例如<0.5mu的熔丝。

95. 发明申请

US20010023975A1 Method of and apparatus for cutting off fuse electrode, integrated circuit device, and method of manufacturing same 失效
标题翻译：用于切断熔丝电极的方法和装置，集成电路装置及其制造方法
公开(公告)号：US20010023975A1
公开(公告)日：2001-09-27
申请号：US09813992
申请日：2001-03-22
发明人： Tomoki Hirota
IPC分类号： H01L021/82
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Adjacent ones of a plurality of fuse electrodes extending parallel to each other are cut off by a laser beam. Cutting positions on the adjacent fuse electrodes are set to positions which are different from each other in a direction in which the fuse electrodes extend. Since the cutting positions on the adjacent fuse electrodes are different from each other, the adjacent fuse electrodes are prevented from being short-circuited by fragments of components thereof that are scattered when the laser beam is applied to cut off the fuse electrodes.
摘要翻译：通过激光束切断彼此平行延伸的多个熔丝电极的相邻的熔丝电极。在相邻的熔丝电极上的切割位置被设定为在熔丝电极延伸的方向上彼此不同的位置。由于相邻的熔丝电极上的切割位置彼此不同，所以防止了相邻的熔丝电极被用于当激光束被施加以截断熔丝电极时被散射的部件碎片短路。

96. 发明申请

US20010019129A1 Contact structure of wiring and a method for manufacturing the same 有权
标题翻译：布线的接触结构及其制造方法
公开(公告)号：US20010019129A1
公开(公告)日：2001-09-06
申请号：US09755193
申请日：2001-01-08
发明人： Chun-Gi You
IPC分类号： H01L021/44 , H01L021/82 , H01L029/04 , H01L029/40 , H01L031/20
CPC分类号： G02F1/13458 , G02F1/1345 , H01L27/124 , H01L29/458 , H01L29/66765
摘要： First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and a thermal treatment process using annealing step is executed. At this time, all or part of aluminum oxide (AlOx) layer having a high resistivity, which is formed on the gate wire and/or the data wire during manufacturing process, may be removed. Then, the passivation layer is patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad, respectively. By removing aluminum oxide (AlOx) layer having a high resistivity, through annealing step, the contact resistance between the metal of aluminum-based material, and IZO may be minimized, because they directly contact each other.
摘要翻译：首先，将由铝基材料制成的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。形成栅绝缘层，依次形成半导体层和欧姆接触层。接下来，沉积包括下层Cr的导体层和铝基材料的上层，并构图以形成包括与栅极线相交的数据线，源电极，漏电极和数据焊盘的数据线。然后，沉积钝化层，并执行使用退火步骤的热处理工艺。此时，可以除去在制造过程中在栅极线和/或数据线上形成的具有高电阻率的全部或部分氧化铝（AlOx）层。然后，对钝化层进行构图以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。接下来，IZO被沉积和图案化以分别形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。通过去除具有高电阻率的氧化铝（AlOx）层，通过退火步骤，铝基材料的金属与IZO之间的接触电阻可以最小化，因为它们彼此直接接触。

97. 发明申请

US20010015441A1 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20010015441A1
公开(公告)日：2001-08-23
申请号：US09732724
申请日：2000-12-11
发明人： Ritsuko Kawasaki , Kenji Kasahara , Hisashi Ohtani
IPC分类号： H01L021/00 , H01L029/76 , H01L031/036 , H01L029/04 , H01L029/82 , H01L021/425 , H01L027/01 , H01L021/84 , H01L029/84 , H01L021/82
CPC分类号： H01L29/78645 , G02F1/13454 , H01L27/12 , H01L27/1281 , H01L29/4908 , H01L29/66757 , H01L29/78624 , H01L29/78648 , H01L29/78675
摘要： To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.
摘要翻译：为了提供可以通过在控制晶片的晶粒的位置和尺寸的同时，通过形成晶体半导体膜来高速操作的TFT，以使用用于TFT的沟道形成区域的晶体半导体膜。代替金属或高导热绝缘膜，仅使用传统的绝缘膜作为基膜来引入温度梯度。基底绝缘膜的电平差设置在所需位置，以根据电平差的布置在半导体膜中产生温度分布。利用温度分布来控制侧向生长的起点和方向。

98. 发明申请

US20040256649A1 Ferroelectric memory device with a conductive polymer layer and a method of formation 失效
公开(公告)号：US20040256649A1
公开(公告)日：2004-12-23
申请号：US10895184
申请日：2004-07-20
发明人： Ebrahim Andideh
IPC分类号： H01L021/82 , H01L031/119
CPC分类号： G11C11/22 , H01L27/11502 , H01L28/60
摘要： A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

99. 发明申请

US20040241915A1 Semiconductor integrated circuit and method of manufacturing the same 审中-公开
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20040241915A1
公开(公告)日：2004-12-02
申请号：US10883723
申请日：2004-07-06
申请人： OKI Electric Industry Co., LTD.
发明人： Kimikatsu Shoji , Hirofumi Tadokoro , Osamu Yanaga
IPC分类号： H01L021/82 , H01L027/10
CPC分类号： H01L27/0207 , H01L27/118 , H01L27/11898 , H01L2224/05554
摘要： A semiconductor integrated circuit includes a plurality of functional blocks placed on a semiconductor chip and being respectively provided with predetermined functions by semiconductor devices and a gate array block placed on said chip. The gate array block includes a plurality of electrically connected basic cells implementing desired functions. The gate array block has a circuit designed after placing the functional blocks and the basic cells on the chip. The functional blocks and gate array block are laid out with at least one common mask in a first area including a center position on a surface of the semiconductor chip. The circuit also includes I/O buffers surrounding the first area.
摘要翻译：半导体集成电路包括放置在半导体芯片上并分别由半导体器件和放置在所述芯片上的栅极阵列块分别设置有预定功能的多个功能块。门阵列块包括实现所需功能的多个电连接的基本单元。门阵列块具有将功能块和基本单元放置在芯片上之后设计的电路。功能块和门阵列块在包括半导体芯片的表面上的中心位置的第一区域中布置有至少一个公共掩模。该电路还包括围绕第一区域的I / O缓冲器。

100. 发明申请

US20040232448A1 Layout style in the interface between input/output (I/O) cell and bond pad 审中-公开
标题翻译：输入/输出（I / O）单元和键盘接口之间的布局样式
公开(公告)号：US20040232448A1
公开(公告)日：2004-11-25
申请号：US10444873
申请日：2003-05-23
申请人： Taiwan Semiconductor Manufacturing Co.
发明人： Tsung-Hsin Yu , Hsien-Chin Chen
IPC分类号： H01L027/10 , H01L021/82 , H01L021/44
CPC分类号： H01L24/02 , H01L23/522 , H01L2224/04042 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/14 , H01L2924/1433
摘要： A layout design for I/O cell area/bond pad area interfaces, and a method of form the same, comprising: a substrate having an I/O cell area and a bond pad area separated by a trench area; and multiple metal lines over the substrate. The multiple metal lines including a lowermost metal line, lower intermediate metal lines, upper intermediate metal lines and an uppermost metal line, wherein at least one of the upper intermediate metal lines includes a respective extension portion, that is contiguous with, or separate therefrom, extending into at least through the trench area.
摘要翻译：用于I / O单元区域/接合焊盘区域界面的布局设计及其形成方法，包括：具有由沟槽区域分隔开的I / O单元区域和接合焊盘区域的基板; 和多个金属线。所述多个金属线包括最下面的金属线，下部中间金属线，上部中间金属线和最上面的金属线，其中至少一个上部中间金属线包括相应的延伸部分，至少延伸穿过沟槽区域。

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