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91. 发明公开

KR20180043578A 리프레쉬 타임 검출회로 및 이를 포함하는 반도체 장치 审中-公开
公开(公告)号：KR20180043578A
公开(公告)日：2018-04-30
申请号：KR20160136448
申请日：2016-10-20
申请人： SK HYNIX INC
发明人： LEE HYENG OUK
IPC分类号： G11C29/08 , G11C11/406 , G11C29/00
CPC分类号： G11C11/4078 , G11C11/403 , G11C11/4072 , G11C29/12015 , G11C29/26 , G11C29/50016 , G11C29/56012 , G11C2029/0403 , G11C2029/5002 , G11C2211/406
摘要： 본발명은리프레쉬타임검출회로및 이를포함하는반도체장치에관한것으로서, 스트레스온도조건에대응하여리프레쉬특성을테스트하기위한기술이다. 이러한본 발명은리프레쉬타임을검출하기위한코드신호를생성하는코드생성부, 패일신호에따라코드신호를래치하여래치신호를생성하고, 프리인에이블신호와포스트인에이블신호에대응하여래치신호를각각래치하여프리코드신호와포스트코드신호를생성하는래치부, 프리코드신호와포스트코드신호를감산하여리프레쉬검출신호를출력하는감산기및 포스트인에이블신호의활성화시리프레쉬검출신호를오프셋신호와비교하여검출신호를생성하는비교기를포함한다.

92. 发明公开

KR1020170046819A 저장된 행 해머 임계값에 기초한 행 해머 모니터링 审中-实审
标题翻译：基于存储行敲击阈值的行锤监控
公开(公告)号：KR1020170046819A
公开(公告)日：2017-05-02
申请号：KR1020177011068
申请日：2013-06-28
申请人： 인텔 코포레이션
发明人： 바인스,쿨지트 , 할버트,존비.
IPC分类号： G11C29/50 , G11C11/406 , G11C11/4078 , G11C11/408 , G06F13/16
CPC分类号： G11C11/40611 , G06F13/1636 , G11C7/24 , G11C11/4078 , G11C11/408 , G11C29/50 , G11C29/50012
摘要： 메모리서브시스템의검출로직은물리적으로인접한행에대한데이터손상위험을야기하는시간윈도우내에서의액세스횟수를표시하는메모리소자에대한임계값을획득한다. 검출로직은메모리소자에대한구성정보를저장하고, 메모리소자자체상의레지스터일수 있고및/또는메모리소자가속한메모리모듈의구성저장장치의엔트리일수 있는레지스터로부터임계값을획득한다. 검출로직은메모리소자의행에대한액세스횟수가임계값을초과하는지여부를결정한다. 액세스횟수가임계값을초과하는것을검출하는것에응답하여, 검출로직은메모리소자로하여금물리적으로인접한희생행을표적으로하는리프레시를수행하게하기위한트리거링을발생할수 있다.
摘要翻译：存储器子系统的检测逻辑获得存储器元件的阈值，该阈值指示时间窗口内的访问次数，其导致物理上相邻行的数据损坏风险。检测逻辑存储用于存储器件的配置信息，并且可以是存储器件本身上的寄存器和/或从寄存器获得阈值，该寄存器可以是存储器件所属的存储器模块的配置存储器中的条目。检测逻辑确定对一行存储器元件的访问次数是否超过阈值。响应于检测到访问次数超过阈值，检测逻辑可以引起触发以使存储器元件执行针对物理上连续的牺牲行的刷新。

93. 发明公开

KR1020030007693A 트랜지스터 어레이에 공급되는 적어도 하나의 바이어스전압을 조절하는 방법, 전압 조절기 회로 및 트랜지스터어레이 소자 失效
标题翻译： 트랜지스터어레이에공급되는적어도하나의바이어스전압을조절하는방법，전압조절기회로및트랜지터터어레이소자
公开(公告)号：KR1020030007693A
公开(公告)日：2003-01-23
申请号：KR1020027015924
申请日：2001-05-25
申请人： 인터내셔널 비지네스 머신즈 코포레이션 , 인피니언 테크놀로지스 노쓰 아메리카 코포레이션
发明人： 엘리스웨인에프 , 리유준 , 수루이스엘 , 바인푸르트너올리버 , 지브라이언엘
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/146 , G11C5/147 , G11C11/4074 , G11C11/4078 , G11C2207/104
摘要： 모니터 트랜지스터 임계 전압의 비율로 트래킹하는 바이어스 전압 조절에 의해 트랜지스터 어레이 소자의 성능이 향상된다. 본 발명의 회로 및 방법은 특히 DRAM 및 임베디드(embedded) DRAM과 같은 트랜지스터 어레이 소자의 성능을 향상시키는데 유용하다. 특히 정상적으로 어레이에 공급되는 적어도 두 개의 바이어스 전이 적어도 하나의 모니터 트랜지스터의 실제 임계 전압의 비율로 트래킹되어 조절될 때 이러한 효과를 얻게 된다. 성능 향상은 신뢰성 향상, 동작 바이어스 조건의 확장, 전력 소비 감소 및 (메모리 셀의 경우) 저장 시간의 증가를 포함한다.
摘要翻译：通过使用跟踪监视器晶体管阈值电压的一部分的偏压调节来获得改进的晶体管阵列器件性能。该电路和方法对于改善诸如DRAM和嵌入式DRAM的晶体管阵列器件的性能特别有用。当通过至少一个监测晶体管的实际阈值电压的一部分跟踪来调节通常提供给阵列的至少两个偏置电压时，尤其可以获得这些益处。性能改进包括改进的可靠性，更宽的操作偏置条件，降低的功耗和（在存储单元的情况下）改进的保留时间。

94. 发明申请

WO2015187606A3 APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY 审中-公开
标题翻译：利用感应电路确定奇偶性的装置和方法
公开(公告)号：WO2015187606A3
公开(公告)日：2017-05-04
申请号：PCT/US2015033651
申请日：2015-06-02
申请人： MICRON TECHNOLOGY INC
发明人： MANNING TROY A , MURPHY RICHARD C
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C7/06 , G06F11/10 , G06F11/1048 , G11C7/10 , G11C7/22 , G11C7/24 , G11C11/4078 , G11C11/4091
摘要： The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.
摘要翻译：本公开包括涉及使用感测电路的奇偶校验确定的设备和方法。示例性方法可以包括使用感测电路来通过确定与数据值的数量对应的奇偶校验值来保护存储在耦合到阵列的感测线的相应数量的存储器单元中的多个数据值，而无需从阵列传输数据通过输入/输出线。例如，奇偶校验值可以由多个XOR操作确定。该方法可以包括将奇偶校验值存储在耦合到感测线的另一存储器单元中。

95. 发明申请

WO2015016918A1 HYBRID SECURE NON-VOLATILE MAIN MEMORY 审中-公开
标题翻译：混合安全非易失性主存储器
公开(公告)号：WO2015016918A1
公开(公告)日：2015-02-05
申请号：PCT/US2013/053046
申请日：2013-07-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： LI, Sheng , CHANG, Jichuan , RANGANATHAN, Parthasarathy , YOON, Doe Hyun
IPC分类号： G11C7/24 , G11C7/10
CPC分类号： G06F21/79 , G06F21/72 , G11C7/1006 , G11C7/24 , G11C11/4078 , G11C13/0004 , G11C13/0059 , G11C14/0036
摘要： According to an example, a hybrid secure non-volatile main memory (HSNVMM) may include a non-volatile memory (NVM) to store a non-working set of memory data in an encrypted format, and a dynamic random-access memory (DRAM) buffer to store a working set of memory data in a decrypted format. A cryptographic engine may selectively encrypt and decrypt memory pages in the working and non-working sets of memory data. A security controller may control memory data placement and replacement in the NVM and the DRAM buffer based on memory data characteristics that include clean memory pages, dirty memory pages, working set memory pages, and non-working set memory pages. The security controller may further provide incremental encryption and decryption instructions to the cryptographic engine based on the memory data characteristics.
摘要翻译：根据示例，混合安全非易失性主存储器（HSNVMM）可以包括以加密格式存储非工作的存储器数据集的非易失性存储器（NVM）和动态随机存取存储器（DRAM））缓冲器以解密的格式存储一组工作的存储器数据。加密引擎可以选择性地加密和解密存储器数据的工作和非工作集合中的存储器页面。安全控制器可以基于包括清洁存储器页面，脏存储器页面，工作集存储器页面和非工作集存储器页面的存储器数据特性来控制NVM和DRAM缓冲器中的存储器数据放置和替换。安全控制器还可以基于存储器数据特性向密码引擎提供增量的加密和解密指令。

96. 发明申请

WO2013002239A1 機器固有情報生成装置と機器固有情報生成方法、端末機器および認証システム审中-公开
标题翻译：装置特定信息产生装置，装置特定信息生成方法，终端装置和认证系统
公开(公告)号：WO2013002239A1
公开(公告)日：2013-01-03
申请号：PCT/JP2012/066331
申请日：2012-06-27
申请人：日本電気株式会社 , 峯松一彦 , 岡村利彦 , 角尾幸保
发明人：峯松　一彦 , 岡村　利彦 , 角尾　幸保
IPC分类号： G06F21/02 , G06F21/20 , G11C11/406
CPC分类号： H04L63/08 , G06F21/30 , G11C11/406 , G11C11/4078 , G11C29/50012 , G11C29/50016 , G11C2029/4402 , G11C2029/5002 , G11C2211/4062 , G11C2211/4065
摘要：　Dynamic Random Access Memory (DRAM)と、DRAMのリフレッシュ処理を停止することによって消失させる消失ビット数の範囲に関する情報を受け、消失ビット数の範囲を達成するようにリフレッシュ処理を停止する時間を制御するリフレッシュ制御部と、リフレッシュ処理の停止で発生した消失ビットの位置情報に基づき機器固有情報を生成する物理情報マッピング部とを備える。リフレッシュ制御部は設定された消失ビット数の範囲を達成するように現在の消失ビット数に基づいて前記リフレッシュ処理を停止する時間を修正することが望ましい。　
摘要翻译：一种装置专用信息产生装置，包括：动态随机存取存储器（DRAM）; 刷新控制单元，其接收与通过中断DRAM的刷新处理而消除的消除的比特数范围有关的信息，并控制刷新处理被中断的定时，从而实现消除的比特数范围; 以及物理信息映射单元，其基于从刷新处理中断产生的消除的位位置信息来生成装置专用信息。优选地，刷新控制单元基于当前消除的比特数来校正刷新处理被中断的定时，使得实现所设置的消除比特数范围。

97. 发明申请

WO2006057794A2 TRANSPARENT ERROR CORRECTING MEMORY THAT SUPPORTS PARTIAL-WORD WRITE 审中-公开
标题翻译：透明错误修正支持部分字写入的记忆
公开(公告)号：WO2006057794A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/040087
申请日：2005-11-03
申请人： MONOLITHIC SYSTEM TECHNOLOGY, INC. , LEUNG, Wingyu
发明人： LEUNG, Wingyu
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： A high-speed partial-word write operation is performed in a memory system. First, an error correction code (ECC) word, which includes a data word and associated error correction bits, is read from a memory array. A word line and a plurality of sense amplifiers are enabled during this read operation. The read data word is corrected in response to the associated error correction bits, thereby creating a corrected data word. The corrected data word is merged with a write data word, thereby creating a merged write data word. Write error correction bits are generated in response to the merged write data word, and the merged write data word and write error correction bits are written to the memory array. The word line and the plurality of sense amplifiers remain enabled from the reading operation through the write operation, thereby speeding up the partial-word write operation.
摘要翻译：在存储器系统中执行高速部分字写入操作。首先，从存储器阵列读取包括数据字和相关联的纠错位的纠错码（ECC）字。在该读取操作期间，字线和多个读出放大器被使能。响应于相关联的纠错位来校正读取的数据字，由此创建校正的数据字。校正的数据字与写入数据字合并，从而创建合并的写入数据字。响应于合并的写入数据字产生写入纠错位，并且将合并的写入数据字和写入错误校正位写入存储器阵列。通过写入操作，字线和多个读出放大器从读取操作保持使能，从而加速部分字写入操作。

98. 发明申请

WO2004097657A2 METHOD AND APPARATUS TO ESTABLISH, REPORT AND ADJUST SYSTEM MEMORY USAGE 审中-公开
标题翻译：建立，报告和调整系统存储器使用的方法和装置
公开(公告)号：WO2004097657A2
公开(公告)日：2004-11-11
申请号：PCT/US2004/008893
申请日：2004-03-24
申请人： INTEL CORPORATION
发明人： VERGIS, George , GUPTE, Nitin , HUANG, Yuchen
IPC分类号： G06F13/16
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/4078 , G11C2211/4067
摘要： A method is described that entails reading information from a non volatile storage or memory resource. The information is a threshold or information from which a threshold can be calculated. The information is particularly tailored for an operating environment that a system memory is recognized as being subjected to. The method also entails causing a memory controller to employ the threshold so as to control a rate at which the memory performs activities. The rate is less than that at which the system memory would experience a functional failure while being subjected to the operating environment.
摘要翻译：描述了需要从非易失性存储器或存储器资源读取信息的方法。信息是可以计算阈值的阈值或信息。该信息特别针对系统存储器被识别为受到的操作环境而定制。该方法还需要使存储器控制器采用阈值，以便控制存储器执行活动的速率。该速率小于在受到操作环境的情况下系统内存将经历功能故障的速率。

99. 发明申请

WO03049118A9 METHOD AND ARCHITECTURE FOR REFRESHING A 1T MEMORY PROPORTIONAL TO TEMPERATURE 审中-公开
公开(公告)号：WO03049118A9
公开(公告)日：2003-12-18
申请号：PCT/US0237984
申请日：2002-11-26
申请人： CYPRESS SEMICONDUCTOR CORP , FISCUS TIMOTHY E
发明人： FISCUS TIMOTHY E
IPC分类号： G11C7/04 , G11C11/406 , G11C11/4078 , G11C7/00
CPC分类号： G11C7/04 , G11C11/406 , G11C11/4078
摘要： An apparatus comprising an array of memory cells (06), a refresh circuit (104), a first monitor cell (110), a second monitor cell (112), and a control circuit (114). The refresh circuit may be configured to refresh the array of memory cells (106) in response to a refresh control signal (REFNOW). The first monitor cell (110) may be configured to have a charge leakage similar to the memory cells. The second monitor cell (112) may be configured to have a discharge leakage similar to the memory cells. The control circuit (114) may be configured to generate the refresh control signal (REFNOW) in response to either a voltage level of the first monitor cell (110) rising above a first pre-determined threshold level or a voltage level of the second monitor cell (112) dropping below a second pre-determined threshold level, where the first and second threshold levels are different.

100. 发明申请

WO2003036850A1 PHASE ADJUSTMENT APPARATUS AND METHOD FOR A MEMORY DEVICE SIGNALING SYSTEM 审中-公开
标题翻译：用于存储器件信号系统的相位调整装置和方法
公开(公告)号：WO2003036850A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/033706
申请日：2002-10-22
申请人： RAMBUS INC.
发明人： HAMPEL, Craig, E. , PEREGO, Richard, E. , SIDIROPOULOS, Stephanos, S. , TSERN, Ely, K. , WARE, Fredrick, A.
IPC分类号： H04L5/16
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) (205) and a second device (such as a memory component) (210) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops (255), for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.
摘要翻译：公开了用于调整数据信号的相位以补偿正常操作期间设备之间的相位偏移变化的装置和方法。数据信号的相位在每个发送数据单元中单独调整，并且通过一组公共的相位矢量时钟信号和相应的时钟周期计数信号在多个数据切片之间接收数据单元。即使当第一设备和第二设备之间的累积延迟在半符号时间间隔期间或更长时间期间，在诸如存储器控制器205的第一设备和诸如存储器组件210的第二设备之间的信号信息的传输也不会发生错误系统的操作。该装置减少了所需的电路，例如锁相环255，用于单独调整每个发射数据单元的相位并在多个数据片之间接收数据单元，这又导致系统的复杂性和成本的降低。

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