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    • 91. 发明授权
    • Cache-MMU system
    • Cache-MMU系统
    • US4899275A
    • 1990-02-06
    • US346251
    • 1989-05-01
    • Howard G. SachsJames Y. ChoWalter H. Hollingsworth
    • Howard G. SachsJames Y. ChoWalter H. Hollingsworth
    • G06F9/38G06F12/08G06F12/10
    • G06F9/3814G06F12/0848G06F12/0862G06F12/1054G06F9/3802
    • A cache and memory management system architecture and associated protocol is disclosed. The cache and memory management system is comprised of a set associative memory cache subsystem, a set associative translation logic memory subsystem, hardwired page translation, selectable access mode logic, and selectively enableable instruction prefetch logic. The cache and memory management system includes a system interface for coupling to a systems bus to which a main memory is coupled, and is also comprised of a processor/cache bus interface for coupling to an external CPU. As disclosed, the cache memory management system can function as either an instruction cache with instruction prefetch capability, and on-chip program counter capabilities, and as a data cache memory management system which has an address register for receiving addresses from the CPU, to initiate a transfer of defined numbers of words of data commencing at the transmitted address.Another novel feature disclosed is the quadword boundary, quadword line registers, and quadword boundary detector subsystem, which accelerates access of data within quadword boundaries, and provides for effective prefetch of sequentially ascending locations of storage instructions or data from the cache memory subsystem.
    • 公开了缓存和存储器管理系统架构及相关协议。 高速缓存和存储器管理系统由组合关联存储器高速缓存子系统,集合关联翻译逻辑存储器子系统,硬连线翻译,可选存取模式逻辑以及选择性使能的指令预取逻辑组成。 高速缓存和存储器管理系统包括用于耦合到与主存储器耦合到的系统总线的系统接口,并且还包括用于耦合到外部CPU的处理器/高速缓存总线接口。 如所公开的,高速缓冲存储器管理系统可以用作具有指令预取能力的指令高速缓存和片上程序计数器能力,以及具有用于从CPU接收地址的地址寄存器的数据高速缓冲存储器管理系统,以启动 在发送的地址开始定义数量的数据字的传输。 公开的另一个新颖特征是四字边界,四字线寄存器和四字边界检测器子系统,其加速了四字边界内的数据访问,并提供了来自高速缓冲存储器子系统的存储指令或数据的顺序上升位置的有效预取。
    • 92. 发明授权
    • Hidden panel connector
    • 隐藏面板连接器
    • US4595115A
    • 1986-06-17
    • US757259
    • 1985-07-22
    • Tam H. Huynh
    • Tam H. Huynh
    • H05K5/02B65D43/14B65D51/04
    • H05K5/0221
    • A hidden panel connector for an electronics enclosure having a removable cover member and a fixed cover member. The fixed cover member is provided with a curved member which projects from the fixed cover member and curves in an upward direction. The removable cover member is provided with a cam member which slideably engages the curved portion so that the removable cover member is vertically rotatable about the fixed cover member. Each cover member has a periphery with lips disposed thereon, which lips engage one another to provide additional stability. Each of the cover members also includes an interlocking member. The interlocking members are engageable with one another to prevent the removable cover member from being vertically displaced from the fixed cover member. The curved cam and interlocking members are integral with and disposed on the inside walls of the fixed and removable cover members to provide a connector hidden on the inside of the electronic enclosure.
    • 一种用于具有可拆卸盖构件和固定盖构件的电子外壳的隐藏面板连接器。 固定盖构件设置有从固定盖构件突出并向上弯曲的弯曲构件。 可拆卸盖构件设置有可滑动地接合弯曲部分的凸轮构件,使得可移除盖构件可围绕固定盖构件竖直旋转。 每个盖构件具有设置在其上的唇缘的周边,该唇部彼此接合以提供额外的稳定性。 每个盖构件还包括互锁构件。 互锁构件可彼此接合以防止可移除的盖构件从固定盖构件垂直移位。 弯曲的凸轮和互锁构件与固定和可移除的盖构件的内壁成一体并且设置在其内壁上,以提供隐藏在电子外壳内侧的连接器。
    • 93. 发明授权
    • Banded vector to raster converter
    • 带状矢量到光栅转换器
    • US4458330A
    • 1984-07-03
    • US263192
    • 1981-05-13
    • Bruce E. ImsandChris L. ThomasDavid D. Dorfmueller
    • Bruce E. ImsandChris L. ThomasDavid D. Dorfmueller
    • G06K15/00G06K15/22G09G5/42G06F5/00
    • G06K15/00G06K15/22G09G5/42G06K2215/0065
    • A vector to raster converter system in which vectors are delivered to the system and stored in a vector memory in groups. Each group includes all vectors which have at least a portion in a particular area of the output plot called a vector band. Vectors are serially read out of the vector memory and converted into a series of coordinates of points along the vector. The coordinates of each point are analyzed to determine if the point lies in a second particular area within the vector band called a raster band. The coordinates in the raster band are stored in a raster memory. After the entire vector band has been rasterized the contents of the raster memory are output to a plotter. The contents of the vector memory is then rasterized again and a determination is made as to whether each pair of coordinates is in the next raster band. This process continues until all of the raster bands in the vector band have been processed. All of the vectors in the next vector band are then loaded into the vector memory and the process continues.
    • 向量到光栅转换器系统,其中向量被分组传送到系统并存储在向量存储器中。 每个组包括在输出图的特定区域中至少有一部分称为矢量带的所有向量。 向量从向量存储器中串行读出,并被转换成沿矢量的一系列点坐标。 分析每个点的坐标以确定该点是否位于称为光栅带的向量频带内的第二特定区域中。 光栅带中的坐标存储在光栅存储器中。 在整个矢量频带已被光栅化之后,光栅存储器的内容被输出到绘图仪。 然后,向量存储器的内容再次被光栅化,并且确定每对坐标是否在下一个光栅带中。 该过程继续,直到已经处理了向量带中的所有光栅带。 然后将下一个向量带中的所有向量载入向量存储器,并且该过程继续。
    • 97. 发明授权
    • Routing method in asymmetric networks
    • 非对称网络中的路由方法
    • US09166906B2
    • 2015-10-20
    • US12334891
    • 2008-12-15
    • Peter Laskowski
    • Peter Laskowski
    • H04L12/721G06F9/48H04L12/751H04L29/08
    • H04L45/26G06F9/4862H04L45/02H04L45/08H04L67/34
    • A method for establishing or reinforcing a path through an asymmetric network of interconnected nodes includes storing navigation data at one or more nodes, for use by an agent in traveling from that node to a subsequent node, while ultimately traveling from a first terminal node (for example, a source node) to a second terminal node (for example, a destination node). As the agent travels from a first terminal node to a second terminal node via an intermediate node, the agent modifies the navigation data intended for use by an agent traveling from the second terminal node to the first terminal node via the intermediate node. Agents traveling complementary routes reinforce each other paths, allowing paths to be determined and reinforced.
    • 用于建立或加强通过互连节点的非对称网络的路径的方法包括在一个或多个节点处存储导航数据,供代理从该节点传播到后续节点时使用,同时最终从第一终端节点传播(用于 例如,源节点)连接到第二终端节点(例如,目的地节点)。 当代理经由中间节点从第一终端节点移动到第二终端节点时,代理修改由第二终端节点经由中间节点移动到第一终端节点的代理所使用的导航数据。 旅行互补路线的代理人相互加强,从而确定和加强路径。
    • 98. 发明授权
    • 3-D model view manipulation apparatus
    • 三维模型视图操纵装置
    • US09035944B2
    • 2015-05-19
    • US12851860
    • 2010-08-06
    • Curtis G. Werline
    • Curtis G. Werline
    • G06T17/00G06T19/20
    • G06T19/20G06T2219/2016
    • A 3-D view manipulation apparatus surrounds a 3-D model displayed on a display device, and allows a user to manipulate the view of the model by manipulating the apparatus, without having to divert the user's view from the model. The apparatus is transparent or semi-transparent, such that all of its surfaces are simultaneously visible. The apparatus may include control features on its surface, edges, or corners to facilitate changing the view of the model to a vantage point from or through that control feature. The apparatus may include a set of orthogonal axes at its center, about which the model may be made to rotate.
    • 3-D视图操纵装置围绕显示装置上显示的3-D模型,并且允许用户通过操纵装置来操纵模型的视图,而不必将模型的用户视图转移出去。 该设备是透明或半透明的,使得其所有表面同时可见。 该装置可以包括其表面,边缘或拐角上的控制特征,以便于将模型的视图从或从该控制特征改变到有利位置。 该装置可以在其中心处包括一组正交轴,模型可围绕该组旋转。
    • 100. 发明授权
    • Apparatus and method for memory error detection
    • 用于存储器错误检测的装置和方法
    • US6158025A
    • 2000-12-05
    • US123339
    • 1998-07-28
    • Matthew BrisseRichard Horney
    • Matthew BrisseRichard Horney
    • G06F11/00G06F11/07G06F11/10G11C29/44G06F11/08
    • G06F11/1044G06F11/073G06F11/0772G06F11/079G06F11/1024G11C29/44G06F11/006
    • A system for detecting and reporting memory errors in error correctable memory in a computer system includes a chipset that utilizes the error correctable memory for creating an error detection signal when a memory error occurs. The error detection signal includes data that may be utilized to identify the error correctable memory having a memory error. The system further includes a motherboard having two or more memory interface slots, where the error correctable memory is coupled with at least one of the interface slots, and each of the at least one slots has a unique slot identification number. The chipset is coupled to the motherboard, and the system further includes a driver coupled to the chipset. The motherboard has at least one register that receives the error detection signal and stores the data in the error detection signal in the at least one register. Furthermore, the driver reads the at least one register to determine which memory interface slot number is coupled with the error correctable memory having the error. The driver then determines the slot number based upon the contents of the at least one register.
    • 用于在计算机系统中检测和报告错误可校正存储器中的存储器错误的系统包括利用可纠错存储器在出现存储器错误时创建错误检测信号的芯片组。 错误检测信号包括可用于识别具有存储器错误的错误可校正存储器的数据。 该系统还包括具有两个或多个存储器接口时隙的主板,其中错误可校正存储器与至少一个接口时隙耦合,并且至少一个时隙中的每一个具有唯一的时隙标识号。 芯片组耦合到母板,并且系统还包括耦合到芯片组的驱动器。 主板具有至少一个接收错误检测信号的寄存器,并将数据存储在至少一个寄存器中的错误检测信号中。 此外,驱动器读取至少一个寄存器以确定哪个存储器接口时隙号与具有该错误的错误可校正存储器耦合。 然后,驾驶员基于至少一个寄存器的内容来确定时隙号。