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1. 发明申请

US20080065748A1 System and Method for Configuring a Storage Area Network 有权
标题翻译：配置存储区域网络的系统和方法
公开(公告)号：US20080065748A1
公开(公告)日：2008-03-13
申请号：US11943387
申请日：2007-11-20
申请人： Matthew Brisse
发明人： Matthew Brisse
IPC分类号： G06F15/177
CPC分类号： H04L29/06 , H04L67/1097 , H04L69/329
摘要： A system for configuring a storage area network (SAN) may include a plurality of selectable SAN elements, and a design module operable to graphically configure selected SAN elements, and a validation engine operable to dynamically validate the configuration of the selected SAN elements. The validation engine may include an element related validation module and a group related validation module. The element related validation module may be configured to validate element to element relationships of connected SAN elements in the configuration of selected SAN elements. The group related validation module may be configured to validate a group of SAN elements in the configuration of selected SAN elements. The validation modules may be arranged such that during validation of the configuration of selected SAN elements, the element related validation module is employed before the group related validation module.
摘要翻译：用于配置存储区域网络（SAN）的系统可以包括多个可选择的SAN元件，以及可操作以图形地配置所选择的SAN元件的设计模块，以及可操作以动态地验证所选择的SAN元件的配置的验证引擎。验证引擎可以包括元素相关的验证模块和组相关的验证模块。元素相关的验证模块可以被配置为在选择的SAN元件的配置中验证所连接的SAN元件的元件到元件的关系。组相关的验证模块可以被配置为在所选择的SAN元件的配置中验证一组SAN元件。验证模块可以被布置为使得在验证所选择的SAN元件的配置期间，元件相关的验证模块在组相关验证模块之前被采用。

2. 发明申请

US20060288185A1 System and method for implementing a common descriptor format 审中-公开
标题翻译：用于实现公共描述符格式的系统和方法
公开(公告)号：US20060288185A1
公开(公告)日：2006-12-21
申请号：US11156154
申请日：2005-06-17
申请人： Matthew Brisse , Winston Bumpus
发明人： Matthew Brisse , Winston Bumpus
IPC分类号： G06F12/00
CPC分类号： G11B27/322
摘要： A system and method is disclosed for the implementation of a common descriptor format for storage data formats regardless of the storage media. An example storage medium using a common descriptor format may comprise data stored on the storage medium and a common descriptor that is associated with the stored data and stored on the storage medium. The common descriptor may include formatting information stored in a standardized format. The formatting information may be sufficient to describe how the data is formatted.
摘要翻译：公开了用于实现用于存储数据格式的公共描述符格式的系统和方法，而不管存储介质如何。使用公共描述符格式的示例性存储介质可以包括存储在存储介质上的数据和与存储的数据相关联并存储在存储介质上的公共描述符。公共描述符可以包括以标准格式存储的格式化信息。格式化信息可能足以描述数据的格式。

3. 发明授权

US6158025A Apparatus and method for memory error detection 失效
标题翻译：用于存储器错误检测的装置和方法
公开(公告)号：US6158025A
公开(公告)日：2000-12-05
申请号：US123339
申请日：1998-07-28
申请人： Matthew Brisse , Richard Horney
发明人： Matthew Brisse , Richard Horney
IPC分类号： G06F11/00 , G06F11/07 , G06F11/10 , G11C29/44 , G06F11/08
CPC分类号： G06F11/1044 , G06F11/073 , G06F11/0772 , G06F11/079 , G06F11/1024 , G11C29/44 , G06F11/006
摘要： A system for detecting and reporting memory errors in error correctable memory in a computer system includes a chipset that utilizes the error correctable memory for creating an error detection signal when a memory error occurs. The error detection signal includes data that may be utilized to identify the error correctable memory having a memory error. The system further includes a motherboard having two or more memory interface slots, where the error correctable memory is coupled with at least one of the interface slots, and each of the at least one slots has a unique slot identification number. The chipset is coupled to the motherboard, and the system further includes a driver coupled to the chipset. The motherboard has at least one register that receives the error detection signal and stores the data in the error detection signal in the at least one register. Furthermore, the driver reads the at least one register to determine which memory interface slot number is coupled with the error correctable memory having the error. The driver then determines the slot number based upon the contents of the at least one register.
摘要翻译：用于在计算机系统中检测和报告错误可校正存储器中的存储器错误的系统包括利用可纠错存储器在出现存储器错误时创建错误检测信号的芯片组。错误检测信号包括可用于识别具有存储器错误的错误可校正存储器的数据。该系统还包括具有两个或多个存储器接口时隙的主板，其中错误可校正存储器与至少一个接口时隙耦合，并且至少一个时隙中的每一个具有唯一的时隙标识号。芯片组耦合到母板，并且系统还包括耦合到芯片组的驱动器。主板具有至少一个接收错误检测信号的寄存器，并将数据存储在至少一个寄存器中的错误检测信号中。此外，驱动器读取至少一个寄存器以确定哪个存储器接口时隙号与具有该错误的错误可校正存储器耦合。然后，驾驶员基于至少一个寄存器的内容来确定时隙号。

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