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1. 发明授权

US4933835A Apparatus for maintaining consistency of a cache memory with a primary memory 失效
标题翻译：用于保持高速缓冲存储器与主存储器的一致性的装置
公开(公告)号：US4933835A
公开(公告)日：1990-06-12
申请号：US300174
申请日：1989-01-19
申请人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
发明人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
IPC分类号： G06F12/08
CPC分类号： G06F12/0848
摘要： A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data cache-MMU's are coupled to the main memory via the system bus for independently storing and outputting digital information to respective mapped addressable very high speed cache memory. The microprocessor is coupled via separate and independent very high speed instruction and data buses to each of the instruction cache-MMU and data cache-MMU, respectively, for processing data received from the data cache-MMU responsive to instructions received from the instruction cache-MMU. The instruction bus and data bus are exclusive and independent of one another, and allow for simultaneous very high-speed transfer. The data cache-MMU and instruction cache-MMU each have separate dedicated system bus interfaces for coupling to the main memory and to other peripheral devices which are coupled to the system bus. Numerous other system elements can also be coupled to the system bus, including an interrupt controller, an I/O processor, a bus arbiter, an array processor, and other peripheral controller devices.
摘要翻译：公开了一种具有用于耦合系统元件的高速系统总线的微处理器系统，并且具有分别连接到可独立操作的指令和数据高速缓存-UUU的单独的超高速指令和数据高速缓存-MMU接口的双总线微处理器。主存储器耦合到系统总线，用于选择性地存储和输出数字信息。指令和数据高速缓存MMU经由系统总线耦合到主存储器，用于独立地将数字信息存储并输出到相应的可映射的可寻址的非常高速的高速缓冲存储器。微处理器分别通过单独和独立的非常高速的指令和数据总线耦合到指令高速缓存-MMU和数据高速缓存-MUU中的每一个，用于响应于从指令高速缓冲存储器MMU接收的指令来处理从数据高速缓存MMU接收的数据。 MMU。指令总线和数据总线是独立的并且彼此独立，并且允许同时进行非常高速的传输。数据高速缓存-MMU和指令高速缓存-MUU各自具有单独的专用系统总线接口，用于耦合到主存储器和耦合到系统总线的其它外围设备。许多其他系统元件也可以耦合到系统总线，包括中断控制器，I / O处理器，总线仲裁器，阵列处理器和其它外围控制器设备。

2. 发明授权

US4884197A Method and apparatus for addressing a cache memory 失效
标题翻译：用于寻址缓存的方法和装置
公开(公告)号：US4884197A
公开(公告)日：1989-11-28
申请号：US915319
申请日：1986-10-03
申请人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
发明人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
IPC分类号： G06F12/08
CPC分类号： G06F12/0848
摘要： A microprocessor architecture is disclosed having separate very high speed instruction and data interface circuitry for coupling via respective separate very high speed instruction and data interface buses to respective external instruction cache and data cache circuitry. The microprocessor is comprised of an instruction interface, a data interface, and an execution unit. The instruction interface controls communications with the external instruction cache and couples the instructions from the instruction cache to the microprocessor at very high speed. The data interface controls communications with the external data cache and communicates data bidirectionally at very high speed between the data cache and the microprocessor. The execution unit selectively processes the data received via the data interface from the data cache responsive to the execution unit decoding and executing a respective one of the instructions received via the instruction interface from the instruction cache. In one embodiment, the external instruction cache is comprised of a program counter and addressable memory for outputting stored instructions responsive to its program counter and to an instruction cache advance signal output from the instruction interface. Circuitry in the instruction interface selectively outputs an initial instruction address for storage in the instruction cache program counter responsive to a context switch or branch, such that the instruction interface repetitively couples a plurality of instructions from the instruction cache to the microprocessor responsive to the cache advance signal, independent of and without the need for any intermediate or further address output from the instruction interface to the instruction cache except upon the occurrence of another context switch or branch.
摘要翻译：公开了一种具有单独的非常高速度的指令和数据接口电路的微处理器架构，用于经由相应的单独的非常高速的指令和数据接口总线耦合到相应的外部指令高速缓存和数据高速缓微处理器由指令接口，数据接口和执行单元构成。指令接口控制与外部指令高速缓存的通信，并以非常高的速度将指令从指令高速缓存耦合到微处理器。数据接口控制与外部数据缓存的通信，并以非常高的速度在数据高速缓存和微处理器之间双向传送数据。响应于执行单元解码，执行单元选择性地处理经由数据接口从数据高速缓存接收的数据，并且执行经由指令接口从指令高速缓存接收的相应指令。在一个实施例中，外部指令高速缓存由程序计数器和可寻址存储器组成，用于响应于其程序计数器输出存储的指令，以及从指令接口输出的指令高速缓存提前信号。响应于上下文切换或分支，指令接口中的电路有选择地输出用于存储在指令高速缓存程序计数器中的初始指令地址，使得指令接口响应于高速缓存提前将多条指令从指令高速缓存耦合到微处理器信号，独立于且不需要从指令接口输出到指令高速缓存的任何中间或另外的地址，除了发生另一个上下文切换或分支之外。

3. 发明授权

US4860192A Quadword boundary cache system 失效
标题翻译：四边形边界缓存系统
公开(公告)号：US4860192A
公开(公告)日：1989-08-22
申请号：US915274
申请日：1986-10-03
申请人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
发明人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3814 , G06F12/0848 , G06F12/0862 , G06F12/1054 , G06F9/3802
摘要： In a cache memory system, multiple-word boundary registers, multiple-word line registers, and a multiple-word boundary detector system provide accelerated access of data contained within the cache memory within the multiple-word boundaries, and provides for effective prefetch of sequentially ascending locations of stored data from the cache memory. In an illustrated embodiment, the cache memory stores four words per addressable line of cache storage, and accordingly quad-word boundary registers determine boundary limits on quad-words, quad-word line registers store, in parallel, a selected line from the cache memory, and a quad-word boundary detector system determines when to prefetch the next set of quad-words from the cache memory for storage in the quad-word line registers.
摘要翻译：在高速缓冲存储器系统中，多字边界寄存器，多字行寄存器和多字边界检测器系统提供了包含在多字边界内的高速缓冲存储器内的数据的加速访问，并提供顺序的有效预取来自高速缓冲存储器的存储数据的上升位置。在所示实施例中，高速缓冲存储器存储每个可寻址的高速缓冲存储器行的四个字，因此四字边界寄存器确定四字的边界限制，四字行寄存器并行存储来自高速缓冲存储器，并且四字边界检测器系统确定何时从高速缓冲存储器预取下一组四字，以存储在四字行寄存器中。

4. 发明授权

US4899275A Cache-MMU system 失效
标题翻译： Cache-MMU系统
公开(公告)号：US4899275A
公开(公告)日：1990-02-06
申请号：US346251
申请日：1989-05-01
申请人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
发明人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3814 , G06F12/0848 , G06F12/0862 , G06F12/1054 , G06F9/3802
摘要： A cache and memory management system architecture and associated protocol is disclosed. The cache and memory management system is comprised of a set associative memory cache subsystem, a set associative translation logic memory subsystem, hardwired page translation, selectable access mode logic, and selectively enableable instruction prefetch logic. The cache and memory management system includes a system interface for coupling to a systems bus to which a main memory is coupled, and is also comprised of a processor/cache bus interface for coupling to an external CPU. As disclosed, the cache memory management system can function as either an instruction cache with instruction prefetch capability, and on-chip program counter capabilities, and as a data cache memory management system which has an address register for receiving addresses from the CPU, to initiate a transfer of defined numbers of words of data commencing at the transmitted address.Another novel feature disclosed is the quadword boundary, quadword line registers, and quadword boundary detector subsystem, which accelerates access of data within quadword boundaries, and provides for effective prefetch of sequentially ascending locations of storage instructions or data from the cache memory subsystem.
摘要翻译：公开了缓存和存储器管理系统架构及相关协议。高速缓存和存储器管理系统由组合关联存储器高速缓存子系统，集合关联翻译逻辑存储器子系统，硬连线翻译，可选存取模式逻辑以及选择性使能的指令预取逻辑组成。高速缓存和存储器管理系统包括用于耦合到与主存储器耦合到的系统总线的系统接口，并且还包括用于耦合到外部CPU的处理器/高速缓存总线接口。如所公开的，高速缓冲存储器管理系统可以用作具有指令预取能力的指令高速缓存和片上程序计数器能力，以及具有用于从CPU接收地址的地址寄存器的数据高速缓冲存储器管理系统，以启动在发送的地址开始定义数量的数据字的传输。公开的另一个新颖特征是四字边界，四字线寄存器和四字边界检测器子系统，其加速了四字边界内的数据访问，并提供了来自高速缓冲存储器子系统的存储指令或数据的顺序上升位置的有效预取。

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