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91. 发明申请

US20070094561A1 Methods for distribution of test generation programs 有权
标题翻译：分发测试生成程序的方法
公开(公告)号：US20070094561A1
公开(公告)日：2007-04-26
申请号：US11256211
申请日：2005-10-20
申请人： Jon Udell , Chen Wang , Mark Kassab , Janusz Rajski
发明人： Jon Udell , Chen Wang , Mark Kassab , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318314 , G01R31/31707
摘要： As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.
摘要翻译：如本文所述，电路测试算法或其部分可以以分布式方式执行，使得它们的执行可以通过处理器的网络。在一个方面，通过这种分布式执行获得的结果被确保与通过以非分布式执行它们将获得的结果一致。因此，在一个方面，算法或其部分必须被分配。算法或其部分通过将其随机数生成与彼此独立地分离来实现。该隔离也适用于与相同算法的不同调用实例相关联的任何随机数生成。在一个方面，通过确保用于算法或其部分的随机数序列的计算不依赖于为其他人计算的随机数序列或相同算法的呼叫实例之间的计算来实现隔离。

92. 发明申请

US20070011530A1 Decompressor/PRPG for applying pseudo-random and deterministic test patterns 有权
标题翻译：解压缩器/ PRPG用于应用伪随机和确定性测试模式
公开(公告)号：US20070011530A1
公开(公告)日：2007-01-11
申请号：US11502655
申请日：2006-08-11
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
摘要翻译：微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。解压缩器/ PRPG有两个操作阶段。在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

93. 发明申请

US20070011527A1 Generating responses to patterns stimulating an electronic circuit with timing exception paths 有权
标题翻译：产生对具有定时异常路径刺激电子电路的模式的响应
公开(公告)号：US20070011527A1
公开(公告)日：2007-01-11
申请号：US11478120
申请日：2006-06-28
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

94. 发明授权

US07093175B2 Decompressor/PRPG for applying pseudo-random and deterministic test patterns 有权
公开(公告)号：US07093175B2
公开(公告)日：2006-08-15
申请号：US10736966
申请日：2003-12-15
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

95. 发明申请

US20050240887A1 Generating test patterns having enhanced coverage of untargeted defects 有权
标题翻译：生成具有增强的非目标缺陷覆盖度的测试模式
公开(公告)号：US20050240887A1
公开(公告)日：2005-10-27
申请号：US10979496
申请日：2004-11-01
申请人： Janusz Rajski , Huaxing Tang , Chen Wang
发明人： Janusz Rajski , Huaxing Tang , Chen Wang
IPC分类号： G01R31/3183 , G06F7/60 , G06F11/00 , G06F17/50
CPC分类号： G01R31/31835 , G06F11/263
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are determined. Additional test values that increase detectability of one or more untargeted defects during testing are determined. One or more test patterns are created that include at least a portion of the deterministic test values and at least a portion of the additional test values. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or comprising test patterns generated by any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于生成具有检测无目标缺陷的能力增加的测试图案的方法，装置和系统的代表性实施例。在一个示例性实施例中，例如，确定用于测试集成电路设计中的目标故障（例如，卡住故障或桥接故障）的一个或多个确定性测试值。确定在测试期间增加一个或多个非靶向缺陷的可检测性的附加测试值。创建一个或多个测试模式，其包括确定性测试值的至少一部分和附加测试值的至少一部分。还公开了包括用于使计算机执行任何公开的方法或包括由所公开的任何实施例产生的测试模式的计算机可执行指令的计算机可读介质。

96. 发明授权

US06684358B1 Decompressor/PRPG for applying pseudo-random and deterministic test patterns 有权
标题翻译：解压缩器/ PRPG用于应用伪随机和确定性测试模式
公开(公告)号：US06684358B1
公开(公告)日：2004-01-27
申请号：US09713664
申请日：2000-11-15
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R3128
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
摘要翻译：微芯片上的解压缩器/ PRPG执行伪随机测试模式生成和解码芯片上的电路不足测试的确定性测试模式。解压缩器/ PRPG有两个操作阶段。在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

97. 发明授权

US6070261A Multi-phase test point insertion for built-in self test of integrated circuits 失效
标题翻译：集成电路内置自检的多相测试点插入
公开(公告)号：US6070261A
公开(公告)日：2000-05-30
申请号：US24962
申请日：1998-02-11
申请人： Nagesh Tamarapalli , Janusz Rajski
发明人： Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/263 , G01R31/318342 , G06F17/5022 , G06F2217/14
摘要： Method and apparatus for providing high quality Built-In-Self-Test (BIST) of integrated circuits, while guaranteeing convergence and reducing area-overhead and power dissipation during test mode. A divide and conquer approach is used to partition the test into multiple phases during which a number of test patterns are applied to a circuit under test (CUT). The design of each phase (the selection of control and observation points) is guided by a progressively reduced list of undetected faults. Within a phase, a set of control points maximally contributing to the fault coverage achieved so far is identified using a unique probabilistic fault simulation (PFS) technique. The PFS technique accurately computes a propagation profile of the circuit and uses it to determine the impact of a new control point in the presence of control points selected so far. In this manner, in each new phase a group of control points, driven by fixed values and operating synergistically, is enabled. Observation points are selected in a similar fashion to further enhance the fault coverage. The sets of control and observation points are then inserted into the circuit under test and a new, reduced list of undetected faults is determined through exact fault simulation. This process is iterative and continues until the number of undetected faults is less than or equal to an acceptable threshold, a pre-specified number of control and observation points have been inserted, or the maximum number of specified test phases has been reached.
摘要翻译：提供集成电路的高质量内置自检（BIST）的方法和装置，同时保证在测试模式下的融合并减少面积开销和功耗。分割和征服方法用于将测试分成多个阶段，在此阶段将多个测试模式应用于被测电路（CUT）。每个阶段的设计（控制和观测点的选择）都是逐渐减少的未检测到的故障列表。在一个阶段中，使用独特的概率故障模拟（PFS）技术来识别到目前为止所达到的最大限度地有助于故障覆盖的一组控制点。 PFS技术准确地计算电路的传播特性，并使用它来确定在目前为止选择的控制点存在时新控制点的影响。以这种方式，在每个新阶段，启用由固定值驱动并且协同操作的一组控制点。以类似的方式选择观测点，以进一步增强故障覆盖。然后将控制和观测点的集合插入到被测电路中，并通过精确的故障模拟确定未被检测的故障的新的减少的列表。该过程是迭代的，并且持续到未检测到的故障的数量小于或等于可接受的阈值，已经插入了预定数量的控制和观察点，或者达到了指定的测试阶段的最大数目。

98. 发明授权

US10955460B2 Test scheduling and test access in test compression environment 有权
公开(公告)号：US10955460B2
公开(公告)日：2021-03-23
申请号：US13635683
申请日：2011-03-16
申请人： Mark Kassab , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Jakub Janicki , Jerzy Tyszer
发明人： Mark Kassab , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Jakub Janicki , Jerzy Tyszer
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3185 , G01R31/3183
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.

99. 发明申请

US20180143249A1 SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST 审中-公开
公开(公告)号：US20180143249A1
公开(公告)日：2018-05-24
申请号：US15875589
申请日：2018-01-19
申请人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee
发明人： Janusz Rajski , Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee
IPC分类号： G01R31/317 , G06F11/27 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

100. 发明申请

US20150285854A1 Test Scheduling and Test Access in Test Compression Environment 审中-公开
标题翻译：测试压缩环境中的测试调度和测试访问
公开(公告)号：US20150285854A1
公开(公告)日：2015-10-08
申请号：US13635683
申请日：2011-03-16
申请人： Mark A. Kassab , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Jakub Janicki , Tyszer Jerzy
发明人： Mark A. Kassab , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Jakub Janicki , Tyszer Jerzy
IPC分类号： G01R31/28
CPC分类号： G01R31/2834 , G01R31/2851 , G01R31/318335 , G01R31/318547 , G01R31/31921
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
摘要翻译：公开了测试压缩环境中用于测试调度和测试访问的方法，装置和系统的代表性实施例。基于包括压缩测试数据，对应的测试仪通道要求和相关核心的测试信息形成用于测试电路中的多个核心的测试模式的集群。测试模式集群的形成之后是测试者信道分配。可以采用最佳拟合方案或平衡拟合方案来产生信道分配信息。可以基于信道分配信息来设计用于动态信道分配的测试接入电路。

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