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1. 发明申请

US20090327986A1 GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS 有权
标题翻译：对具有定时异常电位的电子电路刺激模式的响应
公开(公告)号：US20090327986A1
公开(公告)日：2009-12-31
申请号：US12494121
申请日：2009-06-29
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G06F17/50
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

2. 发明授权

US07984354B2 Generating responses to patterns stimulating an electronic circuit with timing exception paths 有权
标题翻译：产生对具有定时异常路径刺激电子电路的模式的响应
公开(公告)号：US07984354B2
公开(公告)日：2011-07-19
申请号：US12494121
申请日：2009-06-29
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

3. 发明授权

US07555689B2 Generating responses to patterns stimulating an electronic circuit with timing exception paths 有权
标题翻译：产生对具有定时异常路径刺激电子电路的模式的响应
公开(公告)号：US07555689B2
公开(公告)日：2009-06-30
申请号：US11478120
申请日：2006-06-28
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更精确地确定传播到电路中的观测点的未知值来捕获具有定时异常路径的电子电路设计来扫描图案（例如，测试图案）以改善响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

4. 发明申请

US20070011527A1 Generating responses to patterns stimulating an electronic circuit with timing exception paths 有权
标题翻译：产生对具有定时异常路径刺激电子电路的模式的响应
公开(公告)号：US20070011527A1
公开(公告)日：2007-01-11
申请号：US11478120
申请日：2006-06-28
申请人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
发明人： Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/318583
摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
摘要翻译：可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

5. 发明授权

US08051352B2 Timing-aware test generation and fault simulation 有权
标题翻译：定时识别测试生成和故障模拟
公开(公告)号：US08051352B2
公开(公告)日：2011-11-01
申请号：US11796374
申请日：2007-04-27
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

6. 发明授权

US10509073B2 Timing-aware test generation and fault simulation 有权
公开(公告)号：US10509073B2
公开(公告)日：2019-12-17
申请号：US15664169
申请日：2017-07-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/3183 , G01R31/3177 , G06F17/50
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

7. 发明授权

US08560906B2 Timing-aware test generation and fault simulation 有权
公开(公告)号：US08560906B2
公开(公告)日：2013-10-15
申请号：US13285899
申请日：2011-10-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

8. 发明申请

US20120174049A1 TIMING-AWARE TEST GENERATION AND FAULT SIMULATION 有权
标题翻译：定时测试生成和故障模拟
公开(公告)号：US20120174049A1
公开(公告)日：2012-07-05
申请号：US13285899
申请日：2011-10-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G06F17/50
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

9. 发明申请

US20070288822A1 Timing-aware test generation and fault simulation 有权
标题翻译：定时识别测试生成和故障模拟
公开(公告)号：US20070288822A1
公开(公告)日：2007-12-13
申请号：US11796374
申请日：2007-04-27
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G06F9/455 , G01R31/3183
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

10. 发明申请

US20180045780A1 TIMING-AWARE TEST GENERATION AND FAULT SIMULATION 审中-公开
公开(公告)号：US20180045780A1
公开(公告)日：2018-02-15
申请号：US15664169
申请日：2017-07-31
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/3183 , G01R31/3177 , G06F17/50
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

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