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91. 发明授权

US06329267B1 Isolation region forming methods 失效
公开(公告)号：US06329267B1
公开(公告)日：2001-12-11
申请号：US09520739
申请日：2000-03-07
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L21762
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

92. 发明授权

US06284641B1 Method of forming a contact using a sacrificial spacer 有权
标题翻译：使用牺牲间隔物形成接触的方法
公开(公告)号：US06284641B1
公开(公告)日：2001-09-04
申请号：US09174300
申请日：1998-10-16
申请人： Kunal R. Parekh
发明人： Kunal R. Parekh
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76855 , H01L21/76882 , H01L21/76885 , H01L21/76897 , H01L27/10852 , H01L27/10885 , H01L27/10888
摘要： Disclosed is a method of forming a self-aligned contact to a semiconductor substrate by use of a sacrificial spacer. The sacrificial spacer has the advantage of self aligning metallization to the semiconductive substrate or to a polysilicon plug material without extra photolithography steps as are required in the prior art.
摘要翻译：公开了通过使用牺牲间隔物形成与半导体衬底的自对准接触的方法。牺牲间隔物具有如下优点，即在现有技术中需要的不需要额外的光刻步骤的情况下，将金属化自对准至半导体衬底或多晶硅插塞材料。

93. 发明授权

US06238999B1 Isolation region forming methods 有权
标题翻译：隔离区形成方法
公开(公告)号：US06238999B1
公开(公告)日：2001-05-29
申请号：US09520288
申请日：2000-03-07
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L21762
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

94. 发明授权

US06238971B1 Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures 失效
标题翻译：电容器结构，DRAM单元结构和集成电路，以及形成电容器结构，集成电路和DRAM单元结构的方法
公开(公告)号：US06238971B1
公开(公告)日：2001-05-29
申请号：US08798242
申请日：1997-02-11
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L21/76895 , H01L27/10811 , H01L27/10855 , H01L28/84 , Y10S438/964
摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node. The invention also includes a DRAM cell comprising: a) a bitline node and a capacitor node electrically connected together through a transistor gate; b) a capacitor electrically connected to the capacitor node, the capacitor comprising; i) a storage node, the storage node in lateral cross-section comprising an outer surface extending over a top of the storage node, along a pair of opposing lateral surfaces of the storage node, and within laterally opposing cavities beneath the storage node; ii) a dielectric layer against the storage node outer surface and extending within the opposing cavities beneath the storage node; and iii) a cell plate layer against the dielectric layer and extending within the opposing cavities beneath the storage node; and c) a bitline electrically connected to the bitline node.
摘要翻译：本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。本发明包括形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。本发明还包括DRAM单元，其包括：a）通过晶体管栅极电连接在一起的位线节点和电容器节点; b）电连接到所述电容器节点的电容器，所述电容器包括： i）存储节点，所述存储节点在横截面中包括沿着所述存储节点的一对相对的侧表面延伸到所述存储节点的顶部的外表面，以及在所述存储节点下方的横向相对的空腔内; ii）抵靠存储节点外表面并在存储节点下面的相对空腔内延伸的电介质层; 以及iii）抵靠所述电介质层并且在所述存储节点下方的相对空腔内延伸的电池板层; 以及c）与所述位线节点电连接的位线。

95. 发明授权

US06207523B1 Methods of forming capacitors DRAM arrays, and monolithic integrated circuits 失效
标题翻译：电容器，DRAM阵列，单片集成电路和形成电容器，DRAM阵列和单片集成电路的方法
公开(公告)号：US06207523B1
公开(公告)日：2001-03-27
申请号：US08887742
申请日：1997-07-03
申请人： Kunal R. Parekh , John K. Zahurak , Phillip G. Wald
发明人： Kunal R. Parekh , John K. Zahurak , Phillip G. Wald
IPC分类号： H01L2120
CPC分类号： H01L27/10888 , H01L27/10852 , H01L27/10855 , H01L28/82 , H01L28/84 , H01L28/90 , H01L29/94 , Y10S438/964
摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.
摘要翻译：本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

96. 发明授权

US06191047B1 Etching process using a buffer layer 有权
标题翻译：蚀刻工艺使用缓冲层
公开(公告)号：US06191047B1
公开(公告)日：2001-02-20
申请号：US09597189
申请日：2000-06-20
申请人： Li Li , Zhiqiang Wu , Kunal R. Parekh
发明人： Li Li , Zhiqiang Wu , Kunal R. Parekh
IPC分类号： H01L2100
CPC分类号： H01L21/76802 , H01L21/31111 , H01L21/76831 , H01L21/76841 , H01L21/76897
摘要： The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material. Where the buffer layer is of a conductive layer, the effect of the second etch is that the insulative layer is substantially undercut due to the etching of the buffer layer and due to selectivity to all other etch-exposed structures upon the semiconductor substrate. The undercut leaves a laterally-oriented second cavity within which lateral surfaces of the buffer layer are exposed. Following the second etch, a method of covering the laterally exposed surfaces of the buffer layer, exposed by the undercut, is chosen in order to isolate the remaining laterally exposed surfaces of the buffer layer. These methods include reflowing the insulative layer to cover the laterally exposed surfaces of the buffer layer, and forming a liner layer in the cavity to cover the laterally exposed surfaces of the buffer layer.
摘要翻译：本发明涉及构建其中半导体衬底上具有用于缓冲层将用作蚀刻均匀性辅助的处理方法中的蚀刻缓冲层的微电子器件。在制造微电子器件的方法中，用蚀刻缓冲层和绝缘层覆盖半导体衬底。通过掩模进行图案化和蚀刻来进行第一蚀刻。第一蚀刻穿透绝缘层，在其中形成空腔，并且对缓冲层是选择性的，以便露出缓冲层。执行对绝缘层和半导体衬底具有选择性的第二蚀刻，并且对缓冲层不是选择性的。缓冲层可以是除了绝缘层的材料以外的类型的绝缘材料，或者缓冲层也可以是导电材料。在缓冲层是导电层的情况下，第二蚀刻的效果是由于缓冲层的蚀刻以及由于对半导体衬底上的所有其它蚀刻暴露结构的选择性而导致的绝缘层基本上被切下。底切留下横向定向的第二腔，其中缓冲层的侧表面露出。在第二蚀刻之后，选择覆盖由底切暴露的缓冲层的横向暴露的表面的方法，以便隔离缓冲层的剩余横向暴露的表面。这些方法包括回流绝缘层以覆盖缓冲层的横向暴露的表面，以及在空腔中形成衬层以覆盖缓冲层的横向暴露的表面。

97. 发明授权

US6077790A Etching process using a buffer layer 失效
公开(公告)号：US6077790A
公开(公告)日：2000-06-20
申请号：US818325
申请日：1997-03-14
申请人： Li Li , Zhiqiang Wu , Kunal R. Parekh
发明人： Li Li , Zhiqiang Wu , Kunal R. Parekh
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76802 , H01L21/31111 , H01L21/76831 , H01L21/76897 , H01L21/76841
摘要： The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material. Where the buffer layer is of a conductive layer, the effect of the second etch is that the insulative layer is substantially undercut due to the etching of the buffer layer and due to selectivity to all other etch-exposed structures upon the semiconductor substrate. The undercut leaves a laterally-oriented second cavity within which lateral surfaces of the buffer layer are exposed. Following the second etch, a method of covering the laterally exposed surfaces of the buffer layer, exposed by the undercut, is chosen in order to isolate the remaining laterally exposed surfaces of the buffer layer. These methods include reflowing the insulative layer to cover the laterally exposed surfaces of the buffer layer, and forming a liner layer in the cavity to cover the laterally exposed surfaces of the buffer layer.

98. 发明授权

US6060351A Process for forming capacitor over bit line memory cell 失效
标题翻译：在位线存储单元上形成电容器的工艺
公开(公告)号：US6060351A
公开(公告)日：2000-05-09
申请号：US998023
申请日：1997-12-24
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L21/8242
CPC分类号： H01L27/10844 , H01L27/10852 , Y10S257/906
摘要： A stacked capacitor memory cell and method for its fabrication including providing a layer of insulation glass over word lines on a silicon semiconductor substrate; self-aligning contact holes at the storage nodes and bit line contact location; providing a blanket layer of polysilicon, then silicide, and then an insulating cap; removing a portion of the insulating cap, silicide and polysilicon to form polysilicon plugs having outward surfaces at an elevation below the surface of the insulating glass, thus forming the bit line, a bit line contact and isolating the storage nodes; and providing a stacked capacitor on top of the bit line and in electrical communication with the storage node contact location through the plugs formed simultaneously with the bit line and bit line contact.
摘要翻译：一种叠层电容器存储单元及其制造方法，包括在硅半导体衬底上的字线上提供绝缘玻璃层; 存储节点和位线接触位置处的自对准接触孔; 提供覆盖层的多晶硅，然后是硅化物，然后是绝缘帽; 去除绝缘帽，硅化物和多晶硅的一部分以形成在绝缘玻璃表面下方的外表面的多晶硅塞，从而形成位线，位线接触并隔离存储节点; 并且在位线顶部提供堆叠的电容器，并通过与位线和位线接触同时形成的插头与存储节点接触位置电连通。

99. 发明授权

US6005268A Integrated circuitry, DRAM cells, capacitors, and methods of forming integrated circuitry, DRAM cells and capacitors 失效
标题翻译：集成电路，DRAM单元，电容器和形成集成电路，DRAM单元和电容器的方法
公开(公告)号：US6005268A
公开(公告)日：1999-12-21
申请号：US884925
申请日：1997-06-30
申请人： Kunal R. Parekh , Angela S. Parekh
发明人： Kunal R. Parekh , Angela S. Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L28/82 , H01L28/84
摘要： The invention includes a number of methods and structures pertaining to integrated circuitry. The invention encompasses a method of forming an integrated circuit comprising: a) forming an insulative material layer over a first node location and a second node location, the insulative material layer having an uppermost surface; and b) forming first and second conductive pedestals extending through the insulative material layer and in electrical connection with the first and second node locations, the conductive pedestals comprising exposed uppermost surfaces which are above the uppermost surface of the insulative material layer. The invention also encompasses an integrated circuit comprising: a) a first node location and a second node location within a semiconductor substrate; b) a transistor gate electrically connecting the first and second node locations; c) an insulative material layer over the semiconductor substrate, the insulative material layer comprising an uppermost surface; d) a first conductive pedestal extending through the insulative material layer and in electrical connection with the first node location; e) a second conductive pedestal extending through the insulative material layer and in electrical connection with the second node location; f) the conductive pedestals comprising uppermost surfaces which are at a common elevational height relative to one another and are above the uppermost surface of the insulative material layer in a region proximate the pedestals.
摘要翻译：本发明包括与集成电路有关的许多方法和结构。本发明包括一种形成集成电路的方法，包括：a）在第一节点位置和第二节点位置上形成绝缘材料层，所述绝缘材料层具有最上表面; 以及b）形成延伸穿过所述绝缘材料层并与所述第一和第二节点位置电连接的第一和第二导电基座，所述导电基座包括在所述绝缘材料层的最上表面之上的暴露的最上表面。本发明还包括一种集成电路，包括：a）半导体衬底内的第一节点位置和第二节点位置; b）电连接第一和第二节点位置的晶体管栅极; c）半导体衬底上的绝缘材料层，所述绝缘材料层包括最上表面; d）延伸穿过所述绝缘材料层并与所述第一节点位置电连接的第一导电基座; e）延伸穿过所述绝缘材料层并与所述第二节点位置电连接的第二导电基座; f）导电基座包括相对于彼此处于共同高度的最上表面，并且在接近基座的区域中在绝缘材料层的最上表面之上。

100. 发明授权

US5918122A Methods of forming integrated circuitry, DRAM cells and capacitors 失效
标题翻译：形成集成电路，DRAM单元和电容器的方法
公开(公告)号：US5918122A
公开(公告)日：1999-06-29
申请号：US799492
申请日：1997-02-11
申请人： Kunal R. Parekh , Angela S. Parekh
发明人： Kunal R. Parekh , Angela S. Parekh
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/82 , H01L28/84
摘要： The invention includes a number of methods and structures pertaining to integrated circuitry. The invention encompasses a method of forming an integrated circuit comprising: a) forming an insulative material layer over a first node location and a second node location, the insulative material layer having an uppermost surface; and b) forming first and second conductive pedestals extending through the insulative material layer and in electrical connection with the first and second node locations, the conductive pedestals comprising exposed uppermost surfaces which are above the uppermost surface of the insulative material layer. The invention also encompasses an integrated circuit comprising: a) a first node location and a second node location within a semiconductor substrate; b) a transistor gate electrically connecting the first and second node locations; c) an insulative material layer over the semiconductor substrate, the insulative material layer comprising an uppermost surface; d) a first conductive pedestal extending through the insulative material layer and in electrical connection with the first node location; e) a second conductive pedestal extending through the insulative material layer and in electrical connection with the second node location; f) the conductive pedestals comprising uppermost surfaces which are at a common elevational height relative to one another and are above the uppermost surface of the insulative material layer in a region proximate the pedestals.
摘要翻译：本发明包括与集成电路有关的许多方法和结构。本发明包括一种形成集成电路的方法，包括：a）在第一节点位置和第二节点位置上形成绝缘材料层，所述绝缘材料层具有最上表面; 以及b）形成延伸穿过所述绝缘材料层并与所述第一和第二节点位置电连接的第一和第二导电基座，所述导电基座包括在所述绝缘材料层的最上表面之上的暴露的最上表面。本发明还包括一种集成电路，包括：a）半导体衬底内的第一节点位置和第二节点位置; b）电连接第一和第二节点位置的晶体管栅极; c）半导体衬底上的绝缘材料层，所述绝缘材料层包括最上表面; d）延伸穿过所述绝缘材料层并与所述第一节点位置电连接的第一导电基座; e）延伸穿过所述绝缘材料层并与所述第二节点位置电连接的第二导电基座; f）导电基座包括相对于彼此处于共同高度的最上表面，并且在接近基座的区域中在绝缘材料层的最上表面之上。

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