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1. 发明授权

US06232176B1 Integrated circuitry, DRAM cells, capacitors, and methods of forming integrated circuitry, DRAM cells and capacitors 有权
标题翻译：集成电路，DRAM单元，电容器和形成集成电路，DRAM单元和电容器的方法
公开(公告)号：US06232176B1
公开(公告)日：2001-05-15
申请号：US09276786
申请日：1999-03-24
申请人： Kunal R. Parekh , Angela S. Parekh
发明人： Kunal R. Parekh , Angela S. Parekh
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L28/82 , H01L28/84
摘要： The invention includes a number of methods and structures pertaining to integrated circuitry. The invention encompasses a method of forming an integrated circuit comprising: a) forming an insulative material layer over a first node location and a second node location, the insulative material layer having an uppermost surface; and b) forming first and second conductive pedestals extending through the insulative material layer and in electrical connection with the first and second node locations, the conductive pedestals comprising exposed uppermost surfaces which are above the uppermost surface of the insulative material layer. The invention also encompasses an integrated circuit comprising: a) a first node location and a second node location within a semiconductor substrate; b) a transistor gate electrically connecting the first and second node locations; c) an insulative material layer over the semiconductor substrate, the insulative material layer comprising an uppermost surface; d) a first conductive pedestal extending through the insulative material layer and in electrical connection with the first node location; e) a second conductive pedestal extending through the insulative material layer and in electrical connection with the second node location; f) the conductive pedestals comprising uppermost surfaces which are at a common elevational height relative to one another and are above the uppermost surface of the insulative material layer in a region proximate the pedestals.
摘要翻译：本发明包括与集成电路有关的许多方法和结构。本发明包括一种形成集成电路的方法，包括：a）在第一节点位置和第二节点位置上形成绝缘材料层，所述绝缘材料层具有最上表面; 以及b）形成延伸穿过所述绝缘材料层并与所述第一和第二节点位置电连接的第一和第二导电基座，所述导电基座包括在所述绝缘材料层的最上表面之上的暴露的最上表面。本发明还包括一种集成电路，包括：a）半导体衬底内的第一节点位置和第二节点位置; b）电连接第一和第二节点位置的晶体管栅极; c）半导体衬底上的绝缘材料层，所述绝缘材料层包括最上表面; d）延伸穿过所述绝缘材料层并与所述第一节点位置电连接的第一导电基座; e）延伸穿过所述绝缘材料层并与所述第二节点位置电连接的第二导电基座; f）导电基座包括相对于彼此处于共同高度的最上表面，并且在接近基座的区域中在绝缘材料层的最上表面之上。

2. 发明授权

US6005268A Integrated circuitry, DRAM cells, capacitors, and methods of forming integrated circuitry, DRAM cells and capacitors 失效
标题翻译：集成电路，DRAM单元，电容器和形成集成电路，DRAM单元和电容器的方法
公开(公告)号：US6005268A
公开(公告)日：1999-12-21
申请号：US884925
申请日：1997-06-30
申请人： Kunal R. Parekh , Angela S. Parekh
发明人： Kunal R. Parekh , Angela S. Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L28/82 , H01L28/84
摘要： The invention includes a number of methods and structures pertaining to integrated circuitry. The invention encompasses a method of forming an integrated circuit comprising: a) forming an insulative material layer over a first node location and a second node location, the insulative material layer having an uppermost surface; and b) forming first and second conductive pedestals extending through the insulative material layer and in electrical connection with the first and second node locations, the conductive pedestals comprising exposed uppermost surfaces which are above the uppermost surface of the insulative material layer. The invention also encompasses an integrated circuit comprising: a) a first node location and a second node location within a semiconductor substrate; b) a transistor gate electrically connecting the first and second node locations; c) an insulative material layer over the semiconductor substrate, the insulative material layer comprising an uppermost surface; d) a first conductive pedestal extending through the insulative material layer and in electrical connection with the first node location; e) a second conductive pedestal extending through the insulative material layer and in electrical connection with the second node location; f) the conductive pedestals comprising uppermost surfaces which are at a common elevational height relative to one another and are above the uppermost surface of the insulative material layer in a region proximate the pedestals.
摘要翻译：本发明包括与集成电路有关的许多方法和结构。本发明包括一种形成集成电路的方法，包括：a）在第一节点位置和第二节点位置上形成绝缘材料层，所述绝缘材料层具有最上表面; 以及b）形成延伸穿过所述绝缘材料层并与所述第一和第二节点位置电连接的第一和第二导电基座，所述导电基座包括在所述绝缘材料层的最上表面之上的暴露的最上表面。本发明还包括一种集成电路，包括：a）半导体衬底内的第一节点位置和第二节点位置; b）电连接第一和第二节点位置的晶体管栅极; c）半导体衬底上的绝缘材料层，所述绝缘材料层包括最上表面; d）延伸穿过所述绝缘材料层并与所述第一节点位置电连接的第一导电基座; e）延伸穿过所述绝缘材料层并与所述第二节点位置电连接的第二导电基座; f）导电基座包括相对于彼此处于共同高度的最上表面，并且在接近基座的区域中在绝缘材料层的最上表面之上。

3. 发明授权

US5918122A Methods of forming integrated circuitry, DRAM cells and capacitors 失效
标题翻译：形成集成电路，DRAM单元和电容器的方法
公开(公告)号：US5918122A
公开(公告)日：1999-06-29
申请号：US799492
申请日：1997-02-11
申请人： Kunal R. Parekh , Angela S. Parekh
发明人： Kunal R. Parekh , Angela S. Parekh
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/82 , H01L28/84
摘要： The invention includes a number of methods and structures pertaining to integrated circuitry. The invention encompasses a method of forming an integrated circuit comprising: a) forming an insulative material layer over a first node location and a second node location, the insulative material layer having an uppermost surface; and b) forming first and second conductive pedestals extending through the insulative material layer and in electrical connection with the first and second node locations, the conductive pedestals comprising exposed uppermost surfaces which are above the uppermost surface of the insulative material layer. The invention also encompasses an integrated circuit comprising: a) a first node location and a second node location within a semiconductor substrate; b) a transistor gate electrically connecting the first and second node locations; c) an insulative material layer over the semiconductor substrate, the insulative material layer comprising an uppermost surface; d) a first conductive pedestal extending through the insulative material layer and in electrical connection with the first node location; e) a second conductive pedestal extending through the insulative material layer and in electrical connection with the second node location; f) the conductive pedestals comprising uppermost surfaces which are at a common elevational height relative to one another and are above the uppermost surface of the insulative material layer in a region proximate the pedestals.
摘要翻译：本发明包括与集成电路有关的许多方法和结构。本发明包括一种形成集成电路的方法，包括：a）在第一节点位置和第二节点位置上形成绝缘材料层，所述绝缘材料层具有最上表面; 以及b）形成延伸穿过所述绝缘材料层并与所述第一和第二节点位置电连接的第一和第二导电基座，所述导电基座包括在所述绝缘材料层的最上表面之上的暴露的最上表面。本发明还包括一种集成电路，包括：a）半导体衬底内的第一节点位置和第二节点位置; b）电连接第一和第二节点位置的晶体管栅极; c）半导体衬底上的绝缘材料层，所述绝缘材料层包括最上表面; d）延伸穿过所述绝缘材料层并与所述第一节点位置电连接的第一导电基座; e）延伸穿过所述绝缘材料层并与所述第二节点位置电连接的第二导电基座; f）导电基座包括相对于彼此处于共同高度的最上表面，并且在接近基座的区域中在绝缘材料层的最上表面之上。

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