专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08673735B2 Semiconductor device and method for making same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08673735B2
公开(公告)日：2014-03-18
申请号：US13617464
申请日：2012-09-14
申请人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/28123 , H01L21/76224 , H01L21/84 , H01L27/11 , H01L27/1203
摘要： A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.
摘要翻译：半导体器件包括具有至少一个氮化物材料衬里隔离腔的衬底; 以及含有铪的电介质填充物，其至少部分地包含在并且至少部分地覆盖所述至少一个氮化物衬里隔离腔的至少一部分。

92. 发明授权

US08354331B2 Multiplying pattern density by single sidewall imaging transfer 有权
公开(公告)号：US08354331B2
公开(公告)日：2013-01-15
申请号：US12628686
申请日：2009-12-01
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L29/66795 , H01L21/0337 , H01L21/3086 , H01L29/66818
摘要： A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.

93. 发明申请

US20110291188A1 STRAINED FINFET 审中-公开
标题翻译：应变FINFET
公开(公告)号：US20110291188A1
公开(公告)日：2011-12-01
申请号：US12787383
申请日：2010-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7853
摘要： A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility.
摘要翻译：描述了FinFET，其包括从共同的含Si层延伸的至少两个翅片和从公共层和翅片的侧壁生长的外延材料，以将应变引入公共层和翅片以增加载流子迁移率。

94. 发明申请

US20110175163A1 FinFET WITH THIN GATE DIELECTRIC LAYER 有权
标题翻译：具有薄栅介质层的FinFET
公开(公告)号：US20110175163A1
公开(公告)日：2011-07-21
申请号：US12688347
申请日：2010-01-15
申请人： Eduard A. Cartier , Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Eduard A. Cartier , Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/785 , H01L29/66795
摘要： A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.
摘要翻译：提供了一种半导体器件，其在一个实施例中包括在电介质表面上方的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区，漏区存在于半导体鳍结构的相对端。具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。至少一个栅极导体层与高k栅极电介质层直接接触。还提供了一种形成上述装置的方法。

95. 发明申请

US20110127582A1 MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER 有权
标题翻译：通过单边形图像传输实现图案密度的多样化
公开(公告)号：US20110127582A1
公开(公告)日：2011-06-02
申请号：US12628686
申请日：2009-12-01
申请人： KANGGUO CHENG , Bruce B. Doris , Ying Zhang
发明人： KANGGUO CHENG , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/772 , H01L21/306 , H01L21/20
CPC分类号： H01L29/66795 , H01L21/0337 , H01L21/3086 , H01L29/66818
摘要： A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to foam at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.
摘要翻译：一种用于制造集成电路的方法包括在待图案化的层上图案化心轴。将掺杂剂注入到心轴的暴露的侧壁中以使至少两个具有至少一个与掺杂层相邻的未掺杂区的掺杂层发泡。选择性地蚀刻去除掺杂层以从未掺杂的区域形成柱。使用柱作为蚀刻掩模蚀刻待图案化的层以形成用于集成电路器件的特征。还公开了一种半导体器件。

96. 发明申请

US20100297837A1 Implantation using a hardmask 有权
标题翻译：使用硬掩模进行植入
公开(公告)号：US20100297837A1
公开(公告)日：2010-11-25
申请号：US12469710
申请日：2009-05-21
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/8234 , H01L21/266
CPC分类号： H01L21/266 , H01L21/823892
摘要： A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate. The two ion implantations may be used to form the two type of CMOS wells.
摘要翻译：公开了一种用于处理CMOS阱的方法，并且使用单个硬掩模执行多个离子注入。该方法包括在衬底上形成和图案化硬掩模，由此硬掩模获得第一开口。衬底可以是半导体衬底。该方法还包括执行第一离子注入，其间在第一开口外部，硬掩模基本上防止离子到达衬底。该方法还涉及以光致抗蚀剂覆盖硬掩模的方式施加光致抗蚀剂，并且其还填充第一开口。然后使用光致抗蚀剂来模拟硬掩模，由此硬掩模获得第二开口。该方法还包括执行第二离子注入，其间在第二开口外部，填充第一开口的硬掩模和光致抗蚀剂基本上防止离子到达衬底。两个离子注入可用于形成两种类型的CMOS阱。

97. 发明授权

US07767503B2 Hybrid SOI/bulk semiconductor transistors 失效
标题翻译：混合SOI /体半导体晶体管
公开(公告)号：US07767503B2
公开(公告)日：2010-08-03
申请号：US12132853
申请日：2008-06-04
申请人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

98. 发明申请

US20090039436A1 High Performance Metal Gate CMOS with High-K Gate Dielectric 审中-公开
标题翻译：具有高K栅介质的高性能金属栅极CMOS
公开(公告)号：US20090039436A1
公开(公告)日：2009-02-12
申请号：US11835320
申请日：2007-08-07
申请人： Bruce B. Doris , Eduard Albert Cartier , Barry Paul Linder , Vijay Narayanan , Vamsi Paruchuri , Mark Todhunter Robson , Michelle L. Steen , Ying Zhang
发明人： Bruce B. Doris , Eduard Albert Cartier , Barry Paul Linder , Vijay Narayanan , Vamsi Paruchuri , Mark Todhunter Robson , Michelle L. Steen , Ying Zhang
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： A CMOS structure is disclosed in which both type of FET devices have gate insulators containing high-k dielectrics, and gates containing metals. The threshold of the two type of devices are adjusted in separate manners. One type of device has its threshold set by exposing the high-k dielectric to oxygen. During the oxygen exposure the other type of device is covered by a stressing dielectric layer, which layer also prevents oxygen penetration to its high-k gate dielectric. The high performance of the CMOS structure is further enhanced by adjusting the effective workfunctions of the gates to near band-edge values both NFET and PFET devices.
摘要翻译：公开了CMOS结构，其中两种类型的FET器件具有包含高k电介质的栅极绝缘体和包含金属的栅极。两种类型的设备的阈值以不同的方式进行调整。一种类型的器件通过将高k电介质暴露于氧气而设置其阈值。在氧暴露期间，另一种类型的器件被应力介电层覆盖，该层还防止氧气渗透到其高k栅极电介质。通过将栅极的有效功函数调整到NFET和PFET器件的近带边缘值，进一步增强了CMOS结构的高性能。

99. 发明申请

US20080280404A1 RESIDUE FREE PATTERNED LAYER FORMATION METHOD APPLICABLE TO CMOS STRUCTURES 有权
标题翻译：适用于CMOS结构的残留层形成方法
公开(公告)号：US20080280404A1
公开(公告)日：2008-11-13
申请号：US11746759
申请日：2007-05-10
申请人： Michael Chudzik , Bruce B. Doris , William K. Henson , Hongwen Yan , Ying Zhang
发明人： Michael Chudzik , Bruce B. Doris , William K. Henson , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/28 , H01L21/02 , H01L21/311
CPC分类号： H01L29/045 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L21/823842 , H01L21/823857 , H01L21/84
摘要： A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different NFET and pFET gate electrode materials.
摘要翻译：形成微电子结构的方法使用位于目标层上的掩模层。可以使用掩模层作为蚀刻掩模来蚀刻目标层，以从目标层形成端部锥形目标层。可以在端部锥形目标层上形成另外的目标层，并用附加掩模层掩模。可以蚀刻附加目标层以形成与端部锥形目标层分离的图案化附加目标层，并且不存在与端部锥形目标层相邻的附加靶层残余物。该方法对于制造包括nFET和pFET栅电极的CMOS结构是有用的，其包括不同的NFET和pFET栅电极材料。

100. 发明授权

US07435652B1 Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET 有权
标题翻译：用于制造多晶硅栅极MOSFET和高K介质金属栅极MOSFET的集成方案
公开(公告)号：US07435652B1
公开(公告)日：2008-10-14
申请号：US11694104
申请日：2007-03-30
申请人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/4966 , H01L21/28194 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.
摘要翻译：公开了用于制造双栅极半导体结构的多重集成方案。通过采用新颖的集成方案，尽管栅极堆叠的组成差异以及蚀刻速率的差异，但是在同一半导体衬底上形成多晶硅栅极MOSFET和高k介质金属栅极MOSFET。对于一种类型的栅电极使用薄多晶硅层，并且在这些集成方案中使用含硅层用于其他类型的栅电极，以平衡不同的蚀刻速率并且能够蚀刻两个不同的栅极堆叠。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式