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91. 发明授权

US5655098A High performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length format 失效
标题翻译：高性能超标量微处理器，包括用于以可变字节长度格式存储的字节对齐cisc指令的电路
公开(公告)号：US5655098A
公开(公告)日：1997-08-05
申请号：US599697
申请日：1996-02-09
申请人： David B. Witt , William M. Johnson
发明人： David B. Witt , William M. Johnson
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3822 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.
摘要翻译：提供了一种超标量微处理器，其包括共享高性能主数据处理总线的整数功能单元和浮点功能单元。整数单元和浮点单元还共享共同的重排序缓冲器，寄存器文件，分支预测单元和所有驻留在同一主数据处理总线上的加载/存储单元。指令和数据高速缓存通过处理其间的通信的内部地址数据总线耦合到主存储器。指令解码器耦合到指令高速缓存，并且能够每个微处理器周期解码多个指令。指令以推测顺序从解码器发出，发出无序，完成无序。指令从重新排序缓冲区中重新排序到寄存器文件。微处理器的功能单元期望地容纳显示多个数据宽度的操作数。通过所公开的超标量微处理器的共享架构来实现微处理器管芯尺寸的高性能和高效率的使用。

92. 发明授权

US5655097A High performance superscalar microprocessor including an instruction cache circuit for byte-aligning CISC instructions stored in a variable byte-length format 失效
标题翻译：高性能超标量微处理器包括用于以可变字节长度格式存储的用于字节对准CISC指令的指令高速缓存电路
公开(公告)号：US5655097A
公开(公告)日：1997-08-05
申请号：US599698
申请日：1996-02-09
申请人： David B. Witt , William M. Johnson
发明人： David B. Witt , William M. Johnson
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F12/04
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3822 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.
摘要翻译：提供了一种超标量微处理器，其包括共享高性能主数据处理总线的整数功能单元和浮点功能单元。整数单元和浮点单元还共享共同的重排序缓冲器，寄存器文件，分支预测单元和所有驻留在同一主数据处理总线上的加载/存储单元。指令和数据高速缓存通过处理其间的通信的内部地址数据总线耦合到主存储器。指令解码器耦合到指令高速缓存，并且能够每个微处理器周期解码多个指令。指令以推测顺序从解码器发出，发出无序，完成无序。指令从重新排序缓冲区中重新排序到寄存器文件。微处理器的功能单元期望地容纳显示多个数据宽度的操作数。通过所公开的超标量微处理器的共享架构来实现微处理器管芯尺寸的高性能和高效率的使用。

93. 发明授权

US5146570A System executing branch-with-execute instruction resulting in next successive instruction being execute while specified target instruction is prefetched for following execution 失效
标题翻译：执行执行分支执行指令的系统，导致下一个连续指令在指定的目标指令被预取以执行以后执行
公开(公告)号：US5146570A
公开(公告)日：1992-09-08
申请号：US547423
申请日：1990-07-03
申请人： Phillip D. Hester , William M. Johnson
发明人： Phillip D. Hester , William M. Johnson
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3842
摘要： A method and apparatus are described for expanding the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method and apparatus are also applicable to the use of branch-with-execute instructions wherein a subject instruction is executed immediately following the branch-with-execute instruction. The execution of this subject instruction before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.
摘要翻译：描述了用于扩展指令预取缓冲器的能力的方法和装置。该方法和装置使得指令预取缓冲器能够区分在指令流中的分支之前发生的旧预取和在指令流中的分支之后发生的新的预取。每当将指令的请求发送到存储器时，就产生一个控制标签。返回指令附加了原始控制标签，然后将其与指令预取缓冲器中的控制标签的当前值进行比较。如果两个值相匹配，则表示分支未发生，仍然需要指令。但是，如果控制标签的两个值不相等，则表示指令流中的分支已经发生，并且不再需要从存储器发送到缓冲区的指令。该方法和装置也适用于使用分支执行指令，其中在分支执行指令之后立即执行主题指令。在分支目标指令之前执行该主题指令使系统处理器在等待分支目标指令时继续运行。

94. 发明授权

US5142672A Data transfer controller incorporating direct memory access channels and address mapped input/output windows 失效
标题翻译：数据传输控制器包含直接存储器访问通道和地址映射输入/输出窗口
公开(公告)号：US5142672A
公开(公告)日：1992-08-25
申请号：US132296
申请日：1987-12-15
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.

95. 发明授权

US5014641A Hazard warning device for vehicles 失效
标题翻译：车辆危险警告装置
公开(公告)号：US5014641A
公开(公告)日：1991-05-14
申请号：US580126
申请日：1990-09-10
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： B62J6/20
CPC分类号： B62J6/20
摘要： A body portion is supported in upright position by a support stem and has wind propelling blades arranged to rotatably drive the body portion when subjected to air currents. The body portion has front and rear surfaces one of which may support a rear view mirror and the other of which may support a reflector. The body portion has a lock nut for holding it stationary on the stem, for allowing rotation thereof when released. The body portion has forward and rearward as well as lateral adjustable positioning on the stem, and the stem has lateral positioning on a bracket that mounts it on a vehicle.
摘要翻译：主体部分由支撑杆支撑在直立位置，并且具有布置成在受到气流时可旋转地驱动主体部分的风力推进叶片。主体部分具有前表面和后表面，其中一个可以支撑后视镜，而另一个可以支撑反射器。主体部分具有用于将其固定在杆上的锁定螺母，用于在释放时允许其旋转。主体部分具有向前和向后以及在杆上的横向可调定位，并且杆在支架上具有侧向定位，将其安装在车辆上。

96. 发明授权

US4947366A Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities 失效
标题翻译：输入/输出控制器包含地址映射的输入/输出窗口，并提前读/写后面的功能
公开(公告)号：US4947366A
公开(公告)日：1990-08-07
申请号：US104722
申请日：1987-10-02
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： G06F13/40
CPC分类号： G06F13/404
摘要： Methods and apparatus are set forth for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. The aforesaid transfer is accomplished in a manner that facilitates communication between the first and second set of devices while insulating the performance of the first set of devices from the comparatively lower performance of the second set of devices. According to the preferred embodiment of the invention, an input/output controller i.e., ("IOC") is disclosed that includes a set of address mapped I/O ports. The I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting IOC interface between the Local Bus and Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The IOC may be used as part of a data transfer controller ("DTC") having other components, such as direct memory access components, or may be used independently for transferring data between unmatched buses in, for example, RISC and non-RISC systems and data transmission systems generally.
摘要翻译：提出了用于将数据传送到第一总线和从第一总线传送数据的方法和装置，包括至少一个中央处理单元（“CPU”）的第一组高性能设备和第二总线，第二总线附设了较低性能的设备。上述传送是以促进第一和第二组设备之间的通信的方式实现的，同时将第一组设备的性能与第二组设备的相对较低性能隔离。根据本发明的优选实施例，公开了包括一组地址映射I / O端口的输入/输出控制器（“IOC”）。 I / O端口可以用于在简化指令集计算机（RISC）系统和通常较低性能的外围总线（RISC）系统中耦合到CPU的高性能信道（以下称为“本地总线”）之间传送数据以下简称“远程总线”）。本地总线和远程总线之间产生的IOC接口允许以不会限制系统性能的方式连接到RISC系统的标准外设的广泛性能范围。 IOC可以用作具有其他组件（诸如直接存储器访问组件）的数据传输控制器（“DTC”）的一部分，或者可以独立地用于在诸如RISC和非RISC系统之间的不匹配总线之间传送数据和数据传输系统。

97. 发明授权

US4878168A Bidirectional serial test bus device adapted for control processing unit using parallel information transfer bus 失效
标题翻译：双向串行测试总线设备适用于使用并行信息传输总线的控制处理单元
公开(公告)号：US4878168A
公开(公告)日：1989-10-31
申请号：US924118
申请日：1986-10-29
申请人： William M. Johnson , Charles G. Wright
发明人： William M. Johnson , Charles G. Wright
IPC分类号： G06F11/267
CPC分类号： G06F11/2221
摘要： In a data processing system, particularly one implemented by a microprocessor, apparatus is provided for bypassing the main parallel information bus between the processor and main storage unit by a serial information bus for testing purposes. Serial test information is applied through the serial information bus to a storage control unit which interfaces the processor and storage unit. The control includes circuitry for converting the information from the serial bus into the parallel format of the data which is provided from the processor along the main parallel bus. The test information applied has the same commands and address structure as the information output from the central processor. As a result, when the serial test information is converted to parallel format, by the apparatus, it will be indistinguishable from parallel data applied directly from the processor along the parallel bus.
摘要翻译：在数据处理系统中，特别是由微处理器实现的设备，用于通过用于测试目的的串行信息总线旁路处理器和主存储单元之间的主并行信息总线的装置。串行测试信息通过串行信息总线应用于接口处理器和存储单元的存储控制单元。控制器包括用于将来自串行总线的信息转换为从处理器沿主并行总线提供的数据的并行格式的电路。所应用的测试信息具有与从中央处理器输出的信息相同的命令和地址结构。结果，当串行测试信息被转换为并行格式时，由该装置将不能从并行总线直接从处理器应用的并行数据区分开来。

98. 发明授权

US4799636A Automatically positioned holder for baby bottles 失效
标题翻译：婴儿奶瓶自动定位支架
公开(公告)号：US4799636A
公开(公告)日：1989-01-24
申请号：US91381
申请日：1987-08-31
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： A61J9/06 , A47D15/00
CPC分类号： A61J9/0638 , A61J9/0684
摘要： A baby bottle holder having an enclosure into which the bottle is inserted. A curved surface of the holder permits rocking of the holder upon the bottle being emptied. A weight in the holder imparts rocking movement to the holder upon termination of nursing effort by the infant. An internal wall of the holder insulates the bottle as well as defines air passageways to ease bottle insertion and removal.
摘要翻译：具有瓶子插入其中的外壳的婴儿奶瓶保持架。支架的弯曲表面允许在瓶子被倒空时摇架支架。持有人的重量在婴儿的护理工作终止时向持有人施加摇摆运动。保持器的内壁使瓶子绝缘，并且限定空气通道以便于瓶子的插入和移除。

99. 发明授权

US4775927A Processor including fetch operation for branch instruction with control tag 失效
标题翻译：处理器包括带控制标签的分支指令的提取操作
公开(公告)号：US4775927A
公开(公告)日：1988-10-04
申请号：US666790
申请日：1984-10-31
申请人： Phillip D. Hester , William M. Johnson
发明人： Phillip D. Hester , William M. Johnson
IPC分类号： G06F9/32 , G06F9/38 , G06F12/02
CPC分类号： G06F9/3804 , G06F9/3842 , G06F9/3889
摘要： A method and apparatus expands the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method and apparatus are also applicable to the use of branch-with-execute instructions wherein a subject instruction is executed immediately following the branch-with-execute instruction. The execution of this subject instruction before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.

100. 发明授权

US4773078A Limited diffraction feedback laser system having a controlled distortion cavity-feedback mirror 失效
$Limited diffraction feedback laser system having a controlled distortion cavity-feedback mirror$
标题翻译：有限衍射反馈激光系统具有受控变形腔反馈反射镜
公开(公告)号：US4773078A
公开(公告)日：1988-09-20
申请号：US791912
申请日：1985-10-28
申请人： William M. Johnson
发明人： William M. Johnson
IPC分类号： H01S3/08 , H01S3/23 , G02B5/08
CPC分类号： H01S3/10092 , H01S3/08059 , H01S3/0805 , H01S3/08068 , H01S3/121
摘要： A low diffraction-feedback high-energy laser system includes an injection laser, a master oscillator power amplifier (MOPA), and means for aligning the injection laser to the MOPA. The alignment means includes a relay mirror and sensor array cooperative to center the injection laser externally of the cavity, and the alignment means further includes a relay mirror and cooperative optics and sensor to center the injection laser interiorly of the cavity. Means are disclosed preferably for balancing the heat distribution on both sides of one cavity mirror of the master oscillator power amplifier cavity to maintain its figure undistorted against thermal loading. A composite sensor for providing a dual-sensing capability is disclosed including a mosaic array and a superposed quad sensor. The master oscillator power amplifier preferably includes a convex and a concave cavity reflector. In one embodiment, an intracavity laser separator is disclosed for providing alignment of the injection laser, and in a further embodiment an extracavity laser separator is disclosed for providing injection laser alignment. In both embodiments, a sensor mounted to the convex reflector is operative to provide a signal indication of cavity turbulence.
摘要翻译：低衍射反馈高能激光系统包括注入激光器，主振荡器功率放大器（MOPA）和用于将注入激光器对准MOPA的装置。对准装置包括中继反射镜和传感器阵列，其协作以使注入激光器在腔体的外部居中，并且对准装置还包括中继反射镜和协调光学器件和传感器，用于使注射激光器在腔体的内部居中。公开的装置优选地用于平衡主振荡器功率放大器腔的一个腔镜的两侧的热分布，以使其图形不变形以抵抗热负载。公开了一种用于提供双重感测能力的复合传感器，其包括马赛克阵列和叠加的四分之一传感器。主振荡器功率放大器优选地包括凸和凹腔反射器。在一个实施例中，公开了腔内激光分离器用于提供注射激光器的对准，并且在另一实施例中，公开了用于提供注射激光对准的腔外激光分离器。在两个实施例中，安装到凸反射器的传感器可操作以提供腔湍流的信号指示。

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