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91. 发明申请

US20050054138A1 Method of fabricating trench isolated cross-point memory array 有权
公开(公告)号：US20050054138A1
公开(公告)日：2005-03-10
申请号：US10971263
申请日：2004-10-21
申请人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , H01L27/24 , H01L21/00
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/72 , G11C2213/77 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

92. 发明申请

US20050037520A1 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
标题翻译：当与高度结晶的种子层集成时，获得PCMO薄膜上的可逆电阻开关的方法
公开(公告)号：US20050037520A1
公开(公告)日：2005-02-17
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David Evans , Sheng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David Evans , Sheng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.
摘要翻译：当与高度结晶的种子层集成时，用于获得PCMO薄膜上的可逆电阻开关的方法包括通过MOCVD沉积高度结晶形式的PCMO的种子层，薄膜的厚度为约50埃至300埃通过旋转涂覆沉积种子层上的第二PCMO薄膜层，其厚度为约500埃至3000埃以形成组合的PCMO层; 通过施加约-4V至-5V之间的脉冲宽度在约75ns至1个音箱之间的负电脉冲来增加半导体器件中组合的PCMO膜的电阻; 并且通过施加脉冲宽度大于2.0个音箱的约+ 2.5V至+ 4V之间的正电脉冲来降低半导体器件中组合的PCMO层的电阻。

93. 发明授权

US06472337B1 Precursors for zirconium and hafnium oxide thin film deposition 有权
标题翻译：锆和氧化铪薄膜沉积的前体
公开(公告)号：US06472337B1
公开(公告)日：2002-10-29
申请号：US10020471
申请日：2001-10-30
申请人： Wei-Wei Zhuang , David R. Evans
发明人： Wei-Wei Zhuang , David R. Evans
IPC分类号： H01L2131
CPC分类号： H01L21/31625 , C01G25/02 , C01G27/02 , C07F7/003 , C23C16/405 , H01L21/02181 , H01L21/02189 , H01L21/02271 , H01L21/0228 , H01L21/3141
摘要： A method of making a precursor for a thin film formed by chemical vapor deposition processes, includes mixing ZCl4 with H(tmhd)3 solvent and benzene to form a solution, where Z is an element taken from the group of elements consisting of hafnium and zirconium; refluxing the solution for twelve hours in an argon atmosphere; removing the solvents via vacuum, thereby producing a solid compound; and sublimating the compound at 200° C. in a near vacuum of 0.1 mmHg. A ZOx precursor, for use in a chemical vapor deposition process, includes a Z-containing compound taken from the group of compounds consisting of ZCl(tmhd)3 and ZCl2(tmhd)2.
摘要翻译：通过化学气相沉积法制备薄膜前体的方法包括将ZCl4与H（tmhd）3溶剂和苯混合形成溶液，其中Z是从由铪和锆组成的元素组成的元素 ; 在氩气氛中回流12小时; 通过真空除去溶剂，从而产生固体化合物; 并在0.1mmHg的接近真空下在200℃升华该化合物。用于化学气相沉积方法的ZOx前体包括从ZCl（tmhd）3和ZCl 2（tmhd）2组成的化合物组中取代的含Z化合物。

94. 发明申请

US20080026494A1 Method of fabricating a terbium-doped electroluminescence device via metal organic deposition processes 审中-公开
标题翻译：通过金属有机沉积工艺制造掺铒电致发光器件的方法
公开(公告)号：US20080026494A1
公开(公告)日：2008-01-31
申请号：US11494181
申请日：2006-07-26
申请人： Wei-Wei Zhuang , Yoshi Ono , Wei Gao , Tingkai Li
发明人： Wei-Wei Zhuang , Yoshi Ono , Wei Gao , Tingkai Li
IPC分类号： H01L21/00
CPC分类号： H05B33/10
摘要： A method of fabricating an electroluminescent device includes preparing a wafer and a doped-silicon oxide precursor solution. The doped-silicon oxide precursor solution is spin coated onto the wafer to form a doped-silicon oxide thin film on the wafer, which is baked at progressively increasing temperatures. The wafer is then rapidly thermally annealed, further annealed in a wet oxygen ambient atmosphere. A transparent top electrode is deposited on the doped-silicon oxide thin film, which is patterned, etched, and annealed. The doped-silicon oxide thin film and the wafer undergo a final annealing step to enhance electroluminescent properties.
摘要翻译：制造电致发光器件的方法包括制备晶片和掺杂的氧化硅前体溶液。将掺杂的氧化硅前体溶液旋涂在晶片上以在晶片上形成掺杂的氧化硅薄膜，其在逐渐升高的温度下烘烤。然后将晶片快速热退火，在湿氧环境气氛中进一步退火。透明的顶部电极沉积在掺杂的氧化硅薄膜上，其被图案化，蚀刻和退火。掺杂氧化硅薄膜和晶片进行最终退火步骤以增强电致发光性能。

95. 发明申请

US20070015329A1 Metal/ZnOx/metal current limiter 有权
标题翻译：金属/ ZnOx /金属限流器
公开(公告)号：US20070015329A1
公开(公告)日：2007-01-18
申请号：US11216398
申请日：2005-08-31
申请人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
发明人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
IPC分类号： H01L21/8242
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

96. 发明申请

US20070010037A1 SUPERLATTICE NANOCRYSTAL SI-SIO2 ELECTROLUMINESCENCE DEVICE 有权
标题翻译：超级纳米晶体Si-SIO2电致发光器件
公开(公告)号：US20070010037A1
公开(公告)日：2007-01-11
申请号：US11175797
申请日：2005-07-05
申请人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang
发明人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang
IPC分类号： H01L21/00
CPC分类号： H01L33/34 , B82Y20/00 , H01L33/0012
摘要： A superlattice nanocrystal Si—SiO2 electroluminescence (EL) device and fabrication method have been provided. The method comprises: providing a Si substrate; forming an initial SiO2 layer overlying the Si substrate; forming an initial polysilicon layer overlying the initial SiO2 layer; forming SiO2 layer overlying the initial polysilicon layer; repeating the polysilicon and SiO2 layer formation, forming a superlattice; doping the superlattice with a rare earth element; depositing an electrode overlying the doped superlattice; and, forming an EL device. In one aspect, the polysilicon layers are formed by using a chemical vapor deposition (CVD) process to deposit an amorphous silicon layer, and annealing. Alternately, a DC-sputtering process deposits each amorphous silicon layer, and following the forming of the superlattice, polysilicon is formed by annealing the amorphous silicon layers. Silicon dioxide can be formed by either thermal annealing or by deposition using a DC-sputtering process.
摘要翻译：已经提供了超晶格纳米晶Si-SiO 2电致发光（EL）器件及其制造方法。该方法包括：提供Si衬底; 形成覆盖Si衬底的初始SiO 2层; 形成覆盖初始SiO 2层的初始多晶硅层; 形成覆盖在初始多晶硅层上的SiO 2层; 重复多晶硅和SiO 2层形成，形成超晶格; 用稀土元素掺杂超晶格; 沉积覆盖掺杂超晶格的电极; 并且形成EL器件。在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层和退火来形成多晶硅层。或者，DC溅射工艺沉积每个非晶硅层，并且在形成超晶格之后，通过退火非晶硅层形成多晶硅。可以通过热退火或通过使用DC溅射工艺的沉积来形成二氧化硅。

97. 发明申请

US20050136602A1 Dual-trench isolated crosspoint memory array 有权
标题翻译：双沟隔离交叉点存储器阵列
公开(公告)号：US20050136602A1
公开(公告)日：2005-06-23
申请号：US11039536
申请日：2005-01-19
申请人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： H01L21/76 , G11C13/00 , H01L21/3205 , H01L21/8246 , H01L23/52 , H01L27/10 , H01L27/105 , H01L27/24 , H01L43/08 , H01L29/02 , H01L21/336 , H01L21/4763 , H01L47/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/101 , H01L27/24
摘要： A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.
摘要翻译：已经提供了存储器阵列双沟槽隔离结构及其形成方法。该方法包括：形成p掺杂硅（p-Si）衬底; 形成覆盖p-Si衬底的n掺杂（n +）Si层; 在形成n + Si位线之前，形成覆盖n + Si层的p + Si层; 形成覆盖p +层的氮化硅层; 形成覆盖所述氮化硅层的顶部氧化物层; 执行顶部氧化物层，氮化硅层，p + Si层和n + Si层的一部分的第一选择性蚀刻，以在位线之间形成n + Si位线和位线沟槽; 形成覆盖多个n掺杂硅（n + Si）位线的金属底部电极阵列，具有中间p掺杂（p +）Si区域; 形成与所述n + Si位线正交并覆盖与所述底部电极相邻并分离所述p + Si区域的多个字线氧化物隔离结构; 形成与n + Si位线正交的多个顶部电极字线，覆盖在底部电极上的插入式存储电阻材料; 并且在字线附近形成氧化物填充的字线沟槽。

98. 发明授权

US06586344B2 Precursors for zirconium and hafnium oxide thin film deposition 失效
公开(公告)号：US06586344B2
公开(公告)日：2003-07-01
申请号：US10261448
申请日：2002-09-30
申请人： Wei-Wei Zhuang , David R. Evans
发明人： Wei-Wei Zhuang , David R. Evans
IPC分类号： G01B533
CPC分类号： H01L21/31625 , C01G25/02 , C01G27/02 , C07F7/003 , C23C16/405 , H01L21/02181 , H01L21/02189 , H01L21/02271 , H01L21/0228 , H01L21/3141
摘要： A method of making a precursor for a thin film formed by chemical vapor deposition processes, includes mixing ZCl4 with H(tmhd)3 solvent and benzene to form a solution, where Z is an element taken from the group of elements consisting of hafnium and zirconium; refluxing the solution for twelve hours in an argon atmosphere; removing the solvents via vacuum, thereby producing a solid compound; and sublimating the compound at 200° C. in a near vacuum of 0.1 mmHg. A ZOx precursor, for use in a chemical vapor deposition process, includes a Z-containing compound taken from the group of compounds consisting of ZCl(tmhd)3 and ZCl2(tmhd)2.

99. 发明申请

US20070284575A1 Metal/semiconductor/metal current limiter 有权
标题翻译：金属/半导体/金属限流器
公开(公告)号：US20070284575A1
公开(公告)日：2007-12-13
申请号：US11893402
申请日：2007-08-15
申请人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
发明人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
IPC分类号： H01L29/12
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

100. 发明申请

US20070054042A1 Method of SrCu2O2 spin-on precursor synthesis and low temperature p-type thin film deposition 审中-公开
标题翻译： SrCu2O2旋涂前驱体合成方法及低温p型薄膜沉积方法
公开(公告)号：US20070054042A1
公开(公告)日：2007-03-08
申请号：US11220885
申请日：2005-09-06
申请人： Wei-Wei Zhuang , Yoshi Ono , Wei Gao
发明人： Wei-Wei Zhuang , Yoshi Ono , Wei Gao
IPC分类号： B05D3/12 , B05D3/02
CPC分类号： C01G3/00 , C01P2002/72 , H01L21/02381 , H01L21/02403 , H01L21/02472 , H01L21/02565 , H01L21/02579 , H01L21/02628
摘要： A method of SrCu2O2 spin-on precursor synthesis and low temperature p-type thin film deposition, includes preparing a wafer to receive a spin-coating thereon; selecting metalorganic compounds to form a SrCu2O2 precursor, mixing and refluxing the metalorganic compounds to form a precursor mixture; filtering the precursor mixture to produce a spin-coating precursor; applying the spin-coating precursor to the wafer in a two-step spin coating procedure; baking the spin-coated wafer using a hot-plate bake to evaporate substantially all of the solvents; and annealing the spin-coated wafer to form a SrCu2O2 layer thereon in a two-step post-anneal process.
摘要翻译： SrCu 2 O 2 O 2旋转前体合成和低温p型薄膜沉积的方法包括制备晶片以在其上接受旋涂; 选择金属有机化合物以形成SrCu 2 O 2 O 2前体，将金属有机化合物混合并回流以形成前体混合物; 过滤前体混合物以产生旋涂前体; 以两步旋涂方法将旋涂前驱体施加到晶片上; 使用热板烘烤烘烤旋涂的晶片以基本上蒸发所有溶剂; 并在两步后退火工艺中退火旋涂晶片以形成SrCu 2 O 2 O 2层。

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