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91. 发明授权

US06228209B1 Equipment for forming a glue layer of an opening 有权
标题翻译：用于形成开口胶层的设备
公开(公告)号：US06228209B1
公开(公告)日：2001-05-08
申请号：US09174993
申请日：1998-10-19
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： C23F102
CPC分类号： H01L21/76865 , C23C14/568 , H01L21/76844
摘要： A fabrication equipment to form an opening plug is provided. The equipment at least includes a load/unload chamber, a degas chamber, an usual sputtering chamber, a radio frequency (RF) sputtering chamber, a physical vapor deposition (PVD) chamber, and a chemical vapor deposition (CVD). The load/unload chamber is used to load a substrate. The degas chamber is used to remove moisture on the substrate. The usual sputtering chamber is used to form an opening on the substrate. The PVD chamber is used to form a first glue layer. The RF sputtering chamber is used to remove an overhang structure on the first glue layer. The CVD chamber is used to form a second glue layer over the first glue layer.
摘要翻译：提供一种形成开口塞的制造设备。该设备至少包括装载/卸载室，脱气室，通常的溅射室，射频（RF）溅射室，物理气相沉积（PVD）室和化学气相沉积（CVD））。加载/卸载室用于装载基板。脱气室用于去除基材上的水分。通常的溅射室用于在基板上形成开口。 PVD室用于形成第一胶层。 RF溅射室用于去除第一胶层上的悬垂结构。 CVD室用于在第一胶层上形成第二胶层。

92. 发明授权

US6156671A Method for improving characteristic of dielectric material 有权
标题翻译：改善介电材料特性的方法
公开(公告)号：US6156671A
公开(公告)日：2000-12-05
申请号：US266177
申请日：1999-03-10
申请人： Ting-Chang Chang , Po-Tsun Liu , Water Lur
发明人： Ting-Chang Chang , Po-Tsun Liu , Water Lur
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/31
CPC分类号： H01L21/02137 , H01L21/02282 , H01L21/0234 , H01L21/3122 , H01L21/31058
摘要： A method for improving a characteristic of a dielectric material. A methylsilsesquioxane having a low dielectric constant is used as a dielectric material. A methylsilsesquioxane film is formed on a substrate. A baking process is performed on the methylsilsesquioxane film, and then a curing process is performed on the methylsilsesquioxane film. Next, a hydrogen plasma treatment is performed on the surface of the methylsilsesquioxane film to prevent the methylsilsesquioxane film from being damaged by oxygen plasma for removing photoresist layer, so that the characteristically low dielectric constant of the methylsilsesquioxane film is maintained.
摘要翻译：一种改善介电材料特性的方法。使用具有低介电常数的甲基倍半硅氧烷作为介电材料。在基板上形成甲基倍半硅氧烷膜。对甲基倍半硅氧烷膜进行烘烤处理，然后对甲基倍半硅氧烷膜进行固化处理。接着，对甲基倍半硅氧烷膜的表面进行氢等离子体处理，以防止甲基倍半硅氧烷膜被除去光致抗蚀剂层的氧等离子体损坏，从而维持甲基硅倍半氧烷薄膜的特性低的介电常数。

93. 发明授权

US6153466A Method for increasing capacitance 失效
标题翻译：增加电容的方法
公开(公告)号：US6153466A
公开(公告)日：2000-11-28
申请号：US96349
申请日：1998-06-12
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/84
摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-SI on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.
摘要翻译：通过沉积掺杂多晶硅层来形成DRAM单元的电容器，图案化掺杂多晶硅层以限定电容器的下电极的范围，然后在层上沉积第一层半球状硅（HSG-Si）的掺杂多晶硅。 HSG-Si的第一层的生长被中断，然后生长第二层HSG-Si。在一个方面，HSG-Si的第一层的生长可以通过冷却沉积衬底或停止沉积一段时间而中断，然后重新开始沉积，以在电极的表面上提供第二层HSG-SI。如果重新开始的增长以独立于第一过程的方式发起，则第一层的增长中断，无论是通过冷却还是延迟，都是足够的; 即第二层HSG-Si独立生长。在本发明的另一方面，可以通过从沉积系统中去除电极并执行回蚀作业来中断第一层的生长。在回蚀作业之后，将电极重新引入沉积系统，并在蚀刻的表面上生长第二层HSG-Si。该纹理硅结构形成DRAM电容器的下电极。

94. 发明授权

US6140227A Method of fabricating a glue layer of contact/via 有权
标题翻译：制造接触/通孔胶层的方法
公开(公告)号：US6140227A
公开(公告)日：2000-10-31
申请号：US200514
申请日：1998-11-25
申请人： Coming Chen , Water Lur
发明人： Coming Chen , Water Lur
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76865 , H01L21/76804 , H01L21/76844 , H01L21/76877
摘要： A method of fabricating a glue layer of a contact/via. A substrate is provided and a contact/via opening is formed within a dielectric layer on the substrate to expose the substrate. A glue layer is formed to cover the contact/via opening and conformal the structure. An RF sputtering process is performed on the substrate to remove an overhang structure on the upper corner of the glue layer while it is formed. A conductive layer is then formed in the contact/via opening to electrically connect to the substrate.
摘要翻译：一种制造接触/通孔的胶层的方法。提供衬底，并且在衬底上的电介质层内形成接触/通孔以暴露衬底。形成胶层以覆盖接触/通孔开口并使结构保形。在基板上进行射频溅射工艺，以在其形成时去除胶层上角上的突出结构。然后在接触/通孔中形成导电层，以电连接至衬底。

95. 发明授权

US6117345A High density plasma chemical vapor deposition process 失效
公开(公告)号：US6117345A
公开(公告)日：2000-09-12
申请号：US958460
申请日：1997-10-28
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/027 , H01L21/316 , H01L21/3213 , H01L21/768 , H01L21/467 , H01L21/308 , H01L21/32 , H01L21/762
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838 , H01L21/0276 , H01L21/32136
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

96. 发明授权

US6100191A Method for forming self-aligned silicide layers on sub-quarter micron VLSI circuits 失效
标题翻译：在二分之一微米VLSI电路上形成自对准硅化物层的方法
公开(公告)号：US6100191A
公开(公告)日：2000-08-08
申请号：US59687
申请日：1998-04-14
申请人： Tony Lin , Water Lur , Jiun-Yuan Wu , Hsiao-Lin Lu
发明人： Tony Lin , Water Lur , Jiun-Yuan Wu , Hsiao-Lin Lu
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/2855
摘要： The present invention discloses a method to manufacture a self-aligned silicide layer on a substrate. A metal oxide semiconductor (MOS) device and a shallow trench are fabricated in the substrate. The device has a gate structure, spacers of the gate structured and doping regions. The shallow trench is refilled with silicon oxide material for isolation. A silicon layer is nonconformally deposited on the top surface of the gate structure, the spacers and the doping regions by using a physical vapor deposition (PVD) process, such as ion metal plasma (IMP) process. The IMP process, like a sputtering process, is to ionize a silicon material or a refractory-metal material to silicon ions or metal ions and the ions are biased to anisotropically deposit on the top surface of the substrate. A refractory metal layer is defined on the top surface of the silicon layer by the IMP technology. A two-step thermal annealing process, such as rapid thermal annealing (RTA) process is performed to convert the silicon layer and the refractory metal layer into a silicide layer. Since the silicon layer serves as a silicon source for the salicide process, the silicide layer can form on the spacers and the silicon oxide material of the trench.
摘要翻译：本发明公开了一种在衬底上制造自对准硅化物层的方法。在衬底中制造金属氧化物半导体（MOS）器件和浅沟槽。器件具有栅极结构，栅极结构和掺杂区域的间隔物。浅沟槽用氧化硅材料再填充以进行隔离。通过使用诸如离子金属等离子体（IMP）工艺的物理气相沉积（PVD）工艺，硅层不均匀地沉积在栅极结构，间隔物和掺杂区域的顶表面上。 IMP工艺，如溅射工艺，是将硅材料或难熔金属材料离子化成硅离子或金属离子，并将离子偏置成各向异性沉积在衬底的顶表面上。难熔金属层通过IMP技术限定在硅层的顶表面上。进行两步热退火处理，例如快速热退火（RTA）工艺，以将硅层和难熔金属层转化为硅化物层。由于硅层用作自对准硅化物工艺的硅源，硅化物层可以形成在间隔物和沟槽的氧化硅材料上。

97. 发明授权

US6063689A Method for forming an isolation 失效
标题翻译：形成隔离的方法
公开(公告)号：US6063689A
公开(公告)日：2000-05-16
申请号：US164924
申请日：1998-10-01
申请人： Coming Chen , Water Lur
发明人： Coming Chen , Water Lur
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： A method for forming a shallow-trench isolation starts with forming a polysilicon layer, which has less stress, as the mask layer for patterning the trench on a provided substrate. An oxide layer is then formed to cover the polysilicon layer and fill the trench. The oxide layer is then removed by first performing a chemical mechanical polishing process to remove a portion of the oxide layer, wherein the remains of the oxide layer still covers the polysilicon layer and fills the trench. After that, an etching back process is performed to remove the oxide layer from the top of the polysilicon layer to form the oxide plug, which is used as an isolation.
摘要翻译：用于形成浅沟槽隔离的方法开始于形成具有较小应力的多晶硅层作为用于在所提供的衬底上图案化沟槽的掩模层。然后形成氧化物层以覆盖多晶硅层并填充沟槽。然后通过首先进行化学机械抛光工艺去除氧化物层的一部分，去除氧化物层，其中氧化物层的残余物仍然覆盖多晶硅层并填充沟槽。之后，进行蚀刻反应处理以从多晶硅层的顶部去除氧化物层，以形成用作隔离的氧化物塞。

98. 发明授权

US6027996A Method of planarizing a pre-metal dielectric layer using chemical-mechanical polishing 失效
标题翻译：使用化学机械抛光对预金属介电层进行平面化的方法
公开(公告)号：US6027996A
公开(公告)日：2000-02-22
申请号：US885173
申请日：1997-06-30
申请人： Jiunh-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Jiunh-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/3105 , H01L21/4763
CPC分类号： H01L21/31053
摘要： A method of planarizing a pre-metal dielectric layer using chemical-mechanical polishing, in order to alleviate the problem of resistance reduction when making products having poly-loads, includes providing a semiconductor substrate with a semiconductor component formed thereabove. A pre-metal dielectric layer is formed above the semiconductor substrate. Thereafter, the pre-metal dielectric layer is planarized using chemical-mechanical polishing. Next, a silicon-rich oxide layer, that has a characteristic gettering property which can be used to compensate for the weakening of the gettering ability of the pre-metal dielectric layer, due to the wearing out of the layer in a chemical-mechanical polishing operation, is formed above the pre-metal dielectric layer.
摘要翻译：使用化学机械抛光来平坦化预金属介电层的方法为了减轻制造具有多重负载的产品时的电阻降低的问题，包括提供半导体衬底上形成有半导体元件的方法。在半导体衬底上形成预金属介电层。此后，使用化学机械抛光对金属前介电层进行平面化。接下来，由于化学机械抛光中的层的磨损，具有特征吸气特性的富硅氧化物层可用于补偿预金属介电层的吸杂能力的弱化操作，形成在预金属介电层的上方。

99. 发明授权

US5981383A Method of fabricating a salicide layer of a device electrode 失效
标题翻译：制造器件电极的自对准硅化物层的方法
公开(公告)号：US5981383A
公开(公告)日：1999-11-09
申请号：US814376
申请日：1997-03-11
申请人： Water Lur , Tony Lin
发明人： Water Lur , Tony Lin
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L29/423 , H01L21/70
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L21/3205 , H01L21/32053 , H01L29/665 , H01L29/42376
摘要： Salicide (self-aligned silicide) structures are formed using a process that does not form oxide spacer structures alongside polysilicon gate electrodes and wiring lines. A shaped polysilicon electrode is formed having protrusions extending beyond the sidewalls of the electrode. LDD source/drain regions are formed by ion implantation using only the polysilicon gate electrode as a mask, thereby forming LDD source drain/regions without using spacer oxide regions. Physical vapor deposition is used to deposit a metal layer having discontinuities at or adjacent the protrusions. A first rapid thermal anneal is performed to cause the metal to form a metal silicide over the polysilicon electrode. Unreacted metal is etched and then a second rapid thermal anneal is performed to convert the metal silicide to its lowest resistivity phase. Gate electrodes and wiring lines having this structure generally are formed having lower stress in the silicide layers, producing salicide structures having lower resistance than gate electrodes and wiring lines formed using conventional salicide techniques.
摘要翻译：使用不与多晶硅栅电极和布线一起形成氧化物间隔结构的工艺来形成硅化物（自对准硅化物）结构。形成具有延伸超过电极侧壁的突起的成形多晶硅电极。通过仅使用多晶硅栅极作为掩模的离子注入形成LDD源极/漏极区域，从而在不使用间隔氧化物区域的情况下形成LDD源极漏极/区域。物理气相沉积用于沉积在突起处或邻近突起处具有不连续性的金属层。进行第一快速热退火以使金属在多晶硅电极上形成金属硅化物。蚀刻未反应的金属，然后进行第二次快速热退火，以将金属硅化物转化为最低电阻率相。具有这种结构的栅极电极和布线通常形成为在硅化物层中具有较低的应力，产生具有比栅电极低的电阻和使用常规自对准硅化物技术形成的布线的硅化物结构。

100. 发明授权

US5976931A Method for increasing capacitance 失效
标题翻译：增加电容的方法
公开(公告)号：US5976931A
公开(公告)日：1999-11-02
申请号：US775813
申请日：1996-12-31
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/84
摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.
摘要翻译：通过沉积掺杂多晶硅层来形成DRAM单元的电容器，图案化掺杂多晶硅层以限定电容器的下电极的范围，然后在层上沉积第一层半球状硅（HSG-Si）的掺杂多晶硅。 HSG-Si的第一层的生长被中断，然后生长第二层HSG-Si。在一个方面，HSG-Si的第一层的生长可以通过冷却沉积衬底或停止沉积一段时间而中断，然后重新沉积以在电极的表面上提供第二层HSG-Si。如果重新开始的增长以独立于第一过程的方式发起，则第一层的增长中断，无论是通过冷却还是延迟，都是足够的; 即第二层HSG-Si独立生长。在本发明的另一方面，可以通过从沉积系统中去除电极并执行回蚀作业来中断第一层的生长。在回蚀作业之后，将电极重新引入沉积系统，并在蚀刻的表面上生长第二层HSG-Si。该纹理硅结构形成DRAM电容器的下电极。

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