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91. 发明申请

US20080114919A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US20080114919A1
公开(公告)日：2008-05-15
申请号：US12013595
申请日：2008-01-14
申请人： Linda Rankin , Paul Pierce , Gregory Dermer , Wen-Hann Wang , Kai Cheng , Richard Hofsheier , Nitin Borkar
发明人： Linda Rankin , Paul Pierce , Gregory Dermer , Wen-Hann Wang , Kai Cheng , Richard Hofsheier , Nitin Borkar
IPC分类号： G06F13/36
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

92. 发明申请

US20070204111A1 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
公开(公告)号：US20070204111A1
公开(公告)日：2007-08-30
申请号：US11790989
申请日：2007-04-30
申请人： Manoj Khare , Faye Briggs , Akhilesh Kumar , Lily Looi , Kai Cheng
发明人： Manoj Khare , Faye Briggs , Akhilesh Kumar , Lily Looi , Kai Cheng
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

93. 发明申请

US20070150672A1 Fully buffered DIMM read data substitution for write acknowledgement 失效
标题翻译：全缓冲DIMM读取数据替代写入确认
公开(公告)号：US20070150672A1
公开(公告)日：2007-06-28
申请号：US11321322
申请日：2005-12-28
申请人： James Alexander , Rajat Agarwal , Bruce Christenson , Kai Cheng
发明人： James Alexander , Rajat Agarwal , Bruce Christenson , Kai Cheng
IPC分类号： G06F13/00
CPC分类号： G06F13/4234 , G06F13/1673
摘要： A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.
摘要翻译：内存控制器使用一种方案来从重放队列中退出两个条目，这是由于单个无错误的响应。有利地，重放队列中的条目可以比常规系统更早地退出，从而最小化重播队列的大小。

94. 发明授权

US07234029B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07234029B2
公开(公告)日：2007-06-19
申请号：US09749660
申请日：2000-12-28
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

95. 发明授权

US06857048B2 Pseudo least-recently-used (PLRU) replacement method for a multi-node snoop filter 有权
标题翻译：用于多节点监听过滤器的伪最近最少使用（PLRU）替换方法
公开(公告)号：US06857048B2
公开(公告)日：2005-02-15
申请号：US10046768
申请日：2002-01-17
申请人： Linda J. Rankin , Kai Cheng
发明人： Linda J. Rankin , Kai Cheng
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/123
摘要： A Snoop Filter for use in a multi-node processor system including different nodes of multiple processors and corresponding processor caches is provided with a Pseudo Least-Recently-Used (PLRU) replacement algorithm to identify a least-recently-used (PLRU) line from the plurality of lines in the cache array for update to reflect lines that are replaced in the processor caches.
摘要翻译：提供了一种用于包括多个处理器和相应的处理器高速缓存的不同节点的多节点处理器系统的窥探过滤器，其具有伪最近使用的（PLRU）替换算法，以从最近最少使用的（PLRU）高速缓存阵列中的多条行用于更新以反映在处理器高速缓存中被替换的行。

96. 发明授权

US06636962B1 Self-initializing chipset 失效
标题翻译：自我初始化芯片组
公开(公告)号：US06636962B1
公开(公告)日：2003-10-21
申请号：US09459743
申请日：1999-12-10
申请人： Jiming Sun , Kai Cheng
发明人： Jiming Sun , Kai Cheng
IPC分类号： G06F9445
CPC分类号： G06F9/4411 , G06F8/60
摘要： A chipset in a computer system is initialized without intervention by the processor, thereby reducing the time required to boot the computer system. The system includes a nonvolatile storage device for storing configuration data for the chipset. Logic circuitry loads the configuration data into configuration registers in the chipset. The storage device and logic circuitry can be integrated into the chipset. A data pump can be used to load the configuration data into the configuration registers by serially pumping configuration data onto a scan line coupled to the configuration registers. In a system having more than one chipset, the chipsets can be initialized simultaneously to further reduce the amount of time required to boot the system. The configuration data can be downloaded into the storage device when the system is manufactured, or it can be downloaded from the processor the first time the system is powered up.
摘要翻译：计算机系统中的芯片组被初始化，而不会被处理器干预，从而减少引导计算机系统所需的时间。该系统包括用于存储芯片组的配置数据的非易失性存储装置。逻辑电路将配置数据加载到芯片组中的配置寄存器中。存储设备和逻辑电路可以集成到芯片组中。数据泵可以用于通过将配置数据串行地泵送到与配置寄存器相连的扫描线上，将配置数据加载到配置寄存器中。在具有多于一个芯片组的系统中，可以同时初始化芯片组，以进一步减少启动系统所需的时间。当制造系统时，配置数据可以下载到存储设备中，或者可以在系统第一次通电时从处理器下载配置数据。

97. 发明授权

US06574219B1 Passive message ordering on a decentralized ring 有权
标题翻译：被动消息在分散的环上排序
公开(公告)号：US06574219B1
公开(公告)日：2003-06-03
申请号：US09130399
申请日：1998-08-06
申请人： Gilbert A. Neiger , Nicholas D. Wade , Kai Cheng
发明人： Gilbert A. Neiger , Nicholas D. Wade , Kai Cheng
IPC分类号： H04J326
CPC分类号： H04L47/10 , H04L12/42 , H04L47/34
摘要： In some embodiments, a computer system includes nodes connected through conductors to form a ring. Messages are transmitted on the ring and at least some of the nodes each include control circuitry to receive the messages in a node reception order that is different for each node and order the messages in a global order that is the same for each node having the control circuitry.
摘要翻译：在一些实施例中，计算机系统包括通过导体连接以形成环的节点。消息在环上传输，并且至少一些节点每个都包括控制电路，以便以每个节点不同的节点接收顺序接收消息，并且以具有控制的每个节点的全局顺序排序消息电路。

98. 发明授权

US5680577A Method and system for processing multiple requests for data residing at the same memory address 失效
标题翻译：用于处理驻留在相同存储器地址的数据的多个请求的方法和系统
公开(公告)号：US5680577A
公开(公告)日：1997-10-21
申请号：US430079
申请日：1995-04-27
申请人： Steven George Aden , Kai Cheng , Jin Chin Wang , Ramanathan Raghavan
发明人： Steven George Aden , Kai Cheng , Jin Chin Wang , Ramanathan Raghavan
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F13/1631 , G06F12/0828
摘要： A method and system for processing multiple requests for data residing at the same memory address. The multiple requests are associated with an individual duplicate bit flag that indicates whether the request can be processed. Thus, manipulation of the duplicate bit flag controls the order of processing for each of the received requests, thereby maintaining data coherency and integrity.
摘要翻译：一种用于处理驻留在相同存储器地址上的数据的多个请求的方法和系统。多个请求与单独的重复位标志相关联，指示是否可以处理该请求。因此，重复位标志的操纵控制每个接收到的请求的处理顺序，从而保持数据一致性和完整性。

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