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91. 发明授权

US5388063A Filter circuit with switchable finite impulse response and infinite impulse response filter characteristics 失效
标题翻译：具有可切换有限脉冲响应和无限脉冲响应滤波器特性的滤波电路
公开(公告)号：US5388063A
公开(公告)日：1995-02-07
申请号：US154036
申请日：1993-11-18
申请人： Sunao Takatori , Makoto Yamamoto
发明人： Sunao Takatori , Makoto Yamamoto
IPC分类号： H03H15/00 , H03H17/02 , H03H17/04 , H03H17/06 , G06F15/31 , G06G7/02
CPC分类号： H03H17/0294
摘要： A filter which can operate as a digital filter of the finite impulse response type or the infinite impulse response type using one circuit. The signal to be filtered is multiplied and added using a first calculation circuit and a second calculation circuit. The outputs of the calculation circuits are added using addition circuits. Either the output of the addition circuit or the input of the first calculation circuit is applied by a switching element to the first calculation circuit.
摘要翻译：可以使用一个电路作为有限脉冲响应类型的数字滤波器或无限脉冲响应类型的滤波器。将要滤波的信号与第一计算电路和第二计算电路相乘并相加。使用加法电路加上运算电路的输出。加法电路的输出或第一计算电路的输入由开关元件施加到第一计算电路。

92. 发明授权

US5373464A CCD array memory device having dual, independent clocks of differing speeds 失效
标题翻译：具有不同速度的双独立时钟的CCD阵列存储器件
公开(公告)号：US5373464A
公开(公告)日：1994-12-13
申请号：US77084
申请日：1993-06-16
申请人： Sunao Takatori , Makoto Yamamoto
发明人： Sunao Takatori , Makoto Yamamoto
IPC分类号： G11C27/04 , G11C11/34
CPC分类号： G11C27/04
摘要： The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption.A memory device according to this invention downsizes a block of a memory cell by circulating data on a plural number of linear CCD arrays which are for storing data by an electric charge on a cell and keeping analog data, which sets a clock generation means for circulating data on all arrays and another clock generation means for circulating at a high speed only the array loops having necessary data.
摘要翻译：本发明提供一种用于防止在多个线性CCD阵列上的数据循环被破坏的存储装置，用于高速访问数据，并且用于减少装置的电力消耗。根据本发明的存储器件通过在多个线性CCD阵列上循环数据来缩小存储器单元的块，这些阵列用于通过单元上的电荷存储数据并保持模拟数据，其设置用于循环的时钟产生装置所有阵列上的数据和另一个用于高速循环仅具有必要数据的阵列环的时钟产生装置。

93. 发明授权

US5363205A Image compressing method compressing an image into a compressed image and error coefficients 失效
标题翻译：图像压缩方法将图像压缩成压缩图像和误差系数
公开(公告)号：US5363205A
公开(公告)日：1994-11-08
申请号：US105058
申请日：1993-08-12
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： H03M7/30 , H04N1/41 , H04N1/411 , H04N7/14 , H04N7/18 , H04N7/26 , H04N1/415 , H04N1/417 , H04N7/13
CPC分类号： H04N19/63
摘要： An image compression method which successively diminishes in size the image to form a compressed image. The compression is done by dividing an image into partial areas with equal size, calculating a mean pixel value in each area, and substituting the mean pixel value into the diminished image. The image is then re-enlarged in the same way, and the enlarged image is compared against the original image to determine error values. The error values and the diminished images are used to represent a compressed version of the original image.
摘要翻译：图像压缩方法，其连续地缩小图像以形成压缩图像。通过将图像划分为相同尺寸的部分区域来进行压缩，计算每个区域中的平均像素值，并将平均像素值代入缩小的图像。然后以相同的方式重新放大图像，并将放大的图像与原始图像进行比较以确定误差值。错误值和减少的图像用于表示原始图像的压缩版本。

94. 发明授权

US5355437A Neural network architecture for pattern recognition 失效
标题翻译：用于模式识别的神经网络架构
公开(公告)号：US5355437A
公开(公告)日：1994-10-11
申请号：US22438
申请日：1993-02-16
申请人： Sunao Takatori , Makoto Yamamoto
发明人： Sunao Takatori , Makoto Yamamoto
IPC分类号： G06N3/04 , G06K9/66
CPC分类号： G06K9/4628 , G06N3/0454 , G06K2209/01
摘要： A data processing system according to the present invention provides a plurality of neural layers with neuron groups, each neuron group having a fixed number of neurons. The neurons of the neuron group each have an output coupled to a neuron of an adjacent neuron layer. Each neuron layer has a plurality of neuron groups, and each neuron group has at least one neuron which also belongs to another neuron group, resulting in an overlap in the neuron groups. The number of neurons in the nth neural layer is determined on the basis of the number of neurons in the (n-1)th layer, the size of the neuron groups, and the degree of overlap between the adjacent neuron groups. In a variation of the data processing system of the present invention, the data processing system comprises a plurality of mutually independent data processing portions, each of which comprises a plurality of neural layers.
摘要翻译：根据本发明的数据处理系统提供具有神经元组的多个神经层，每个神经元组具有固定数量的神经元。神经元组的神经元各自具有耦合到相邻神经元层的神经元的输出。每个神经元层具有多个神经元组，并且每个神经元组具有至少一个也属于另一个神经元组的神经元，导致神经元组中的重叠。基于第（n-1）层中的神经元数目，神经元组的大小和相邻神经元组之间的重叠程度确定第n个神经层中神经元的数量。在本发明的数据处理系统的变型中，数据处理系统包括多个相互独立的数据处理部分，每个数据处理部分包括多个神经层。

95. 发明授权

US5343419A Analog calculation circuit using timers 失效
标题翻译：模拟计算电路使用定时器
公开(公告)号：US5343419A
公开(公告)日：1994-08-30
申请号：US964157
申请日：1992-10-21
申请人： Guoliang Shu , Weikang Yang , Wiwat Wongwarawipat , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shu , Weikang Yang , Wiwat Wongwarawipat , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/24 , G06G7/00
CPC分类号： G06G7/24
摘要： An analog calculation circuit has a circuit input for receiving a first input voltage, a circuit output, a first timer, and a second timer. The first timer has a first capacitive coupler, a first RC circuit, and a first threshold circuit for outputting a first timer output voltage. The first threshold circuit has a first threshold input terminal. The first capacitive coupler has a first capacitive coupler input connected to the circuit input, a second capacitive coupler input, and a first capacitive coupler output connected to the first threshold input terminal. The first RC circuit has a first resistance, a first capacitance, a first RC input for receiving a second input voltage, and a first RC output connected to the second capacitive coupler input. The second timer has a second RC circuit, a second threshold circuit for outputting a second timer output voltage to the second RC circuit, and for receiving the first timer output voltage. The second RC circuit has a second resistance, a second capacitance, a second RC input for receiving a third input voltage, and a second RC output connected to the circuit output. A third timer, similar in design to the first timer may also be used in the calculation circuit.
摘要翻译：模拟计算电路具有用于接收第一输入电压的电路输入端，电路输出端，第一定时器和第二定时器。第一定时器具有第一电容耦合器，第一RC电路和用于输出第一定时器输出电压的第一阈值电路。第一阈值电路具有第一阈值输入端子。第一电容耦合器具有连接到电路输入的第一电容耦合器输入，第二电容耦合器输入和连接到第一阈值输入端的第一电容耦合器输出。第一RC电路具有第一电阻，第一电容，用于接收第二输入电压的第一RC输入和连接到第二电容耦合器输入的第一RC输出。第二定时器具有第二RC电路，第二阈值电路，用于将第二定时器输出电压输出到第二RC电路，并用于接收第一定时器输出电压。第二RC电路具有第二电阻，第二电容，用于接收第三输入电压的第二RC输入和连接到电路输出的第二RC输出。在计算电路中也可以使用第三定时器，其设计类似于第一定时器。

96. 发明授权

US06169771A Matched filter for spread spectrum communication systems and hybrid analog-digital transversal filter 失效
标题翻译：用于扩频通信系统和混合模数转换滤波器的匹配滤波器
公开(公告)号：US06169771A
公开(公告)日：2001-01-02
申请号：US09014264
申请日：1998-01-27
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Xiaoling Oin , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Xiaoling Oin , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H04L2706
CPC分类号： H03H17/0254 , H04B1/7093
摘要： In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sample-and-hold circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sample-and-hold circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is refreshed in the same way.
摘要翻译：一方面，本发明提供一种低功耗匹配滤波器。在A / D转换器转换成数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。移位寄存器级的输出被输入到对应于每一级的XOR电路，从而在输出和对应的扩展码位d1至dN之间执行异或运算。 XOR电路的输出类似地添加到模拟加法器中并从输出端子输出。另一方面，滤波器电路使用模拟运算电路来防止由剩余电荷引起的运算精度降低。输入模拟信号在采样保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并加入加法电路。通过移位寄存器中的系数来防止采样数据传输错误存储。采样保持电路和乘法电路由模拟操作电路形成，并且每个都包括用于消除剩余电荷的开关。正常工作的采样保持电路和乘法电路通过提供更换其功能的电路依次刷新。加法电路以相同的方式刷新。

97. 发明授权

US06031415A Matched filter circuit for spread spectrum communication 失效
标题翻译：用于扩频通信的匹配滤波电路
公开(公告)号：US06031415A
公开(公告)日：2000-02-29
申请号：US733820
申请日：1996-10-18
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
IPC分类号： H04J13/00 , H03H17/02 , H04B1/7093 , H03K5/00 , H03D1/00
CPC分类号： H03H17/0254 , H04B1/707
摘要： The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.
摘要翻译：本发明提供了可用于处理小尺寸电路中的长P / N码的匹配滤波器电路。根据本发明的匹配滤波器电路在所提出的发明中执行以下处理：i）采样和保持电路乘以长码的数量的一部分; ii）乘法器与来自第一乘法器寄存器的采样和保持电路并联输入，其可以容纳与i）中的采样和保持电路的数量一样多的PN码; iii）当存在要被顺序使用的PN码为PN码时，PN码存储在第一乘法器电阻相同容量的第二乘法器寄存器中; 和iv）第二乘法器寄存器中的PN码并行发送到第一乘法器寄存器。 PN码以串行方式输入到第二个乘法器寄存器。

98. 发明授权

US5926512A Matched filter circuit 失效
标题翻译：匹配滤波电路
公开(公告)号：US5926512A
公开(公告)日：1999-07-20
申请号：US735787
申请日：1996-10-23
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori , Mamoru Sawahashi , Fumiyuki Adachi
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori , Mamoru Sawahashi , Fumiyuki Adachi
IPC分类号： H04J13/00 , H03H11/04 , H03H17/02 , H03H19/00 , H04B1/7093 , H03D1/00 , H04L27/06
CPC分类号： H03H11/04 , H03H17/0254 , Y02B60/50
摘要： A matched filter circuit for mobile communications is disclosed. The circuit may be fabricated in a small size using large-scale integration and can perform high-speed processing and double sampling at a reduced rate of power consumption. In one embodiment, a plurality of sampling and holding circuits each including a switch are divided into two groups. A control circuit successively closes one of the switches in the first group every chip time, while successively closing one of the switches in the second group at a timing shifted by one-half chip time from that of the first group, thereby enabling a double-sampling operation. Outputs of the sampling and holding circuits in each group are summed by an analog circuit with a high degree of linearity, resulting in a high processing speed combined with a reduced circuit size and power consumption.
摘要翻译：公开了一种用于移动通信的匹配滤波器电路。该电路可以使用大规模集成在小尺寸上制造，并且可以以降低的功率消耗来执行高速处理和双重采样。在一个实施例中，每个包括开关的多个采样和保持电路被分成两组。控制电路在每个码片时间连续地闭合第一组中的一个开关，同时以与第一组相比半个码片时间偏移的时间顺序地关闭第二组中的一个开关，由此，抽样操作。每个组中的采样和保持电路的输出由具有高线性度的模拟电路相加，导致高处理速度以及减小的电路尺寸和功耗。

99. 发明授权

US5910948A Acquisition scheme and receiver for an asynchronous DS-CDMA cellular communication system 失效
标题翻译：异步DS-CDMA蜂窝通信系统的采集方案和接收机
公开(公告)号：US5910948A
公开(公告)日：1999-06-08
申请号：US955613
申请日：1997-10-22
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori , Mamoru Sawahashi , Fumiyuki Adachi
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori , Mamoru Sawahashi , Fumiyuki Adachi
IPC分类号： H04B1/707 , H04B1/708 , H04B1/7083 , H04B7/26 , H04J13/00 , H04L7/00 , H04W36/00 , H04W48/18 , H04W56/00 , H04B7/216
CPC分类号： H04W48/18 , H04B1/70735 , H04B1/70775 , H04B1/708 , H04B1/7083 , H04B1/7093 , H04B1/7117 , H04B2201/70702 , H04W36/00
摘要： The present invention realizes a rapid and efficient cell search and small-size instrument for an asynchronous DS-CDMA cellular system. This cell search detects the correlation between the received signal and the short code of the control channel, and matched filter 22 detects the maximum electric power correlation peak location. Next, using correlators 28-1 to 28-n which are parallelly set in a plurality for RAKE processing with plurality, identifies the long code that is set in the system with the detected long code timing. After the long code is synchronized, a multipath signal is received using 28-1 to 28-n, and the data is judged by RAKE processing. When peripheral cell search is executed, after long code timing is detected by using matched filter 22, the long code of the candidate peripheral cell is designated using the same matched filter. Handover is safely realized by receiving the signal from the connected base station by correlators 28-1 to 28-n, and the base station signal through handover by 22.
摘要翻译：本发明实现了用于异步DS-CDMA蜂窝系统的快速且有效的小区搜索和小尺寸仪器。该小区搜索检测接收信号与控制信道的短码之间的相关性，匹配滤波器22检测最大功率相关峰位置。接下来，使用多个并行设置为用于RAKE处理的多个的相关器28-1至28-n识别具有检测到的长码定时的系统中设置的长码。在长代码同步之后，使用28-1至28-n接收多路径信号，并且通过RAKE处理来判断数据。当执行外围小区搜索时，在通过使用匹配滤波器22检测长码定时之后，使用相同的匹配滤波器来指定候选周边小区的长码。通过由相关器28-1至28-n接收来自所连接的基站的信号，以及通过22次切换的基站信号来安全地实现切换。

100. 发明授权

US5790590A Matched filter circuit 失效
标题翻译：匹配滤波电路
公开(公告)号：US5790590A
公开(公告)日：1998-08-04
申请号：US740672
申请日：1996-10-31
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori , Mamoru Sawahashi , Fumiyuki Adachi
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori , Mamoru Sawahashi , Fumiyuki Adachi
IPC分类号： H03H15/00 , H03H17/02 , H04B1/7093 , H04J13/00 , H04B15/00
CPC分类号： H04B1/7093
摘要： The present invention has an object to provide a matched filter circuit which is possible to synchronize a spreading code with an input signal. A matched filter according to the present invention samples input signal in response to three clocks from the first to the third shifted by a half cycle of a sampling signal so as to judge whether the sampling clock is ahead or behind of the input signal according to signs of input signal sampled. One clock is selected to be the sampling clock.
摘要翻译：本发明的目的是提供一种可以使扩展码与输入信号同步的匹配滤波器电路。根据本发明的匹配滤波器响应于从第一到第三的三个时钟采样输入信号，移位了采样信号的半个周期，以便根据符号判断采样时钟是否在输入信号的前面或后面的输入信号采样。选择一个时钟作为采样时钟。

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