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91. 发明申请

US20080116529A1 SHALLOW TRENCH ISOLATION STRUCTURE FOR SHIELDING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于半导体器件中的屏蔽带电充电的低温隔离结构
公开(公告)号：US20080116529A1
公开(公告)日：2008-05-22
申请号：US12022202
申请日：2008-01-30
申请人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L29/7833
摘要： A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.
摘要翻译：一种包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构的半导体结构。第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

92. 发明申请

US20080102566A1 MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：多层和晶体平面取向半导体基板
公开(公告)号：US20080102566A1
公开(公告)日：2008-05-01
申请号：US11969279
申请日：2008-01-04
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

93. 发明申请

US20070241412A1 BORDERLESS CONTACT STRUCTURES 有权
标题翻译：无边界接触结构
公开(公告)号：US20070241412A1
公开(公告)日：2007-10-18
申请号：US11679873
申请日：2007-02-28
申请人： Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L27/085
CPC分类号： H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/11 , H01L27/1104
摘要： An SRAM cell. The SRAM cell including: a first gate segment common to a first PFET and a first NFET, a second gate segment common to a second PFET and a second NFET; a first silicide layer contacting a first end of the first gate segment and a drain of the second PFET; a second silicide layer contacting a sidewall contact region of the second gate segment and a drain of the first PFET; a third silicide layer contacting a sidewall contact region of the first gate segment and a drain of the second NFET; a fourth silicide layer contacting a first end of the second gate segment, a drain of the first PFET and a drain of a fourth NFET; and a fifth silicide layer contacting a second end of the first gate segment and a drain of a third NFET.
摘要翻译：一个SRAM单元。该SRAM单元包括：第一PFET和第一NFET公共的第一栅极段，与第二PFET和第二NFET共用的第二栅极段; 接触第一栅极段的第一端和第二PFET的漏极的第一硅化物层; 接触第二栅极段的侧壁接触区域和第一PFET的漏极的第二硅化物层; 接触第一栅极段的侧壁接触区域和第二NFET的漏极的第三硅化物层; 接触第二栅极段的第一端的第四硅化物层，第一PFET的漏极和第四NFET的漏极; 以及接触第一栅极段的第二端和第三NFET的漏极的第五硅化物层。

94. 发明申请

US20070059891A1 Mandrel/trim alignment in SIT processing 有权
标题翻译： SIT处理中的心轴/微调对齐
公开(公告)号：US20070059891A1
公开(公告)日：2007-03-15
申请号：US11226726
申请日：2005-09-14
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Qiqing Ouyang
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Qiqing Ouyang
IPC分类号： H01L21/467
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L29/66795
摘要： Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.
摘要翻译：本文公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，其需要将修剪掩模对准亚光刻特征以形成具有离散片段的硬掩模图案。在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

95. 发明申请

US20060024940A1 Borderless contact structures 失效
公开(公告)号：US20060024940A1
公开(公告)日：2006-02-02
申请号：US10710675
申请日：2004-07-28
申请人： Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/11 , H01L27/1104
摘要： A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon line and a corresponding portion of the insulating sidewall layer in a contact region of the polysilicon line; and (e) forming a silicide layer on the sidewall of the polysilicon line in the contact region. Also an SRAM cell using the borderless contact structure and a method of fabricating the SRAM cell.

96. 发明申请

US20050145803A1 Moving lens for immersion optical lithography 失效
标题翻译：移动透镜用于浸没式光刻
公开(公告)号：US20050145803A1
公开(公告)日：2005-07-07
申请号：US10749638
申请日：2003-12-31
申请人： Mark Hakey , David Horak , Charles Koburger , Peter Mitchell
发明人： Mark Hakey , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： G03F7/20 , H01L21/027 , G01J1/00
CPC分类号： G03F7/70341 , G03F7/70258
摘要： An apparatus for immersion optical lithography having a lens capable of relative movement in synchrony with a horizontal motion of a semiconductor wafer in a liquid environment where the synchronous motion of the lens apparatus and semiconductor wafer advantageously reduces the turbulence and air bubbles associated with a liquid environment. The relative motions of the lens and semiconductor wafer are substantially the same as the scanning process occurs resulting in optimal image resolution with minimal air bubbles, turbulence, and disruption of the liquid environment.
摘要翻译：一种用于浸没式光刻的装置，其具有能够在液晶环境中与半导体晶片的水平运动同步的透镜的透镜，其中透镜装置和半导体晶片的同步运动有利地减少了与液体环境相关的湍流和气泡。透镜和半导体晶片的相对运动基本上与扫描过程相同，导致最小的图像分辨率，最小的气泡，湍流和液体环境的破坏。

97. 发明申请

US20050158673A1 LIQUID-FILLED BALLOONS FOR IMMERSION LITHOGRAPHY 有权
标题翻译：液体填充气体用于浸没光刻
公开(公告)号：US20050158673A1
公开(公告)日：2005-07-21
申请号：US10707894
申请日：2004-01-21
申请人： Mark Hakey , David Horak , Charles Koburger , Peter Mitchell
发明人： Mark Hakey , David Horak , Charles Koburger , Peter Mitchell
IPC分类号： A61B18/18 , G03C5/10 , G03C5/20 , G03F7/20 , H01L21/00
CPC分类号： G03F7/70341 , Y10S438/947
摘要： A liquid-filled balloon may be positioned between a workpiece, such as a semiconductor structure covered with a photoresist, and a lithography light source. The balloon includes a thin membrane that exhibits good optical and physical properties. Liquid contained in the balloon also exhibits good optical properties, including a refractive index higher than that of air. Light from the lithography light source passes through a mask, through a top layer of the balloon membrane, through the contained liquid, through a bottom layer of the balloon membrane, and onto the workpiece where it alters portions of the photoresist. As the liquid has a low absorption and a higher refractive index than air, the liquid-filled balloon system enhances resolution. Thus, the balloon provides optical benefits of liquid immersion without the complications of maintaining a liquid between (and in contact with) a lithographic light source mechanism and workpiece.
摘要翻译：液体填充的球囊可以位于诸如被光致抗蚀剂覆盖的半导体结构的工件和光刻光源之间。气球包括显示出良好的光学和物理性质的薄膜。包含在气囊中的液体也表现出良好的光学性能，包括折射率高于空气的折射率。来自光刻光源的光通过球囊膜的顶层通过所包含的液体通过球囊膜的底层，并穿过其上改变部分光致抗蚀剂的工件。由于液体具有比空气低的吸收和较高的折射率，所以充满液体的球囊系统提高了分辨率。因此，气囊提供液体浸没的光学优点，而没有在平版印刷光源机构和工件之间（并与之接触）之间保持液体的并发症。

98. 发明申请

US20060275706A1 Immersion lithography contamination gettering layer 失效
标题翻译：浸没光刻污染吸气层
公开(公告)号：US20060275706A1
公开(公告)日：2006-12-07
申请号：US11144857
申请日：2005-06-03
申请人： Daniel Corliss , Dario Gil , Dario Goldfarb , Steven Holmes , David Horak , Kurt Kimmel , Karen Petrillo , Dmitriy Shneyder
发明人： Daniel Corliss , Dario Gil , Dario Goldfarb , Steven Holmes , David Horak , Kurt Kimmel , Karen Petrillo , Dmitriy Shneyder
IPC分类号： G03F7/20
CPC分类号： G03F7/2041 , G03F7/11 , Y10S430/162
摘要： A method of forming an image in a photoresist layer. The method includes, providing a substrate; forming the photoresist layer over the substrate; forming a contamination gettering topcoat layer over the photoresist layer, the contamination gettering topcoat layer including one or more polymers and one or more cation complexing agents; exposing the photoresist layer to actinic radiation through a photomask having opaque and clear regions, the opaque regions blocking the actinic radiation and the clear regions being transparent to the actinic radiation, the actinic radiation changing the chemical composition of regions of the photoresist layer exposed to the radiation forming exposed and unexposed regions in the photoresist layer; and removing either the exposed regions of the photoresist layer or the unexposed regions of the photoresist layer. The contamination gettering topcoat layer includes one or more polymers, one or more cation complexing agents and a casting solvent.
摘要翻译：在光致抗蚀剂层中形成图像的方法。该方法包括提供基板; 在衬底上形成光致抗蚀剂层; 在光致抗蚀剂层上形成污染吸气顶涂层，吸收顶涂层的污染物包括一种或多种聚合物和一种或多种阳离子络合剂; 将光致抗蚀剂层暴露于通过具有不透明和透明区域的光掩模的光化辐射，不透明区域阻挡光化辐射，透明区域对于光化辐射是透明的，光化辐射改变曝光于光致抗蚀剂层的光致抗蚀剂层的区域的化学组成在光致抗蚀剂层中形成曝光和未曝光区域的辐射; 以及去除光致抗蚀剂层的曝光区域或光致抗蚀剂层的未曝光区域。污染吸附顶涂层包括一种或多种聚合物，一种或多种阳离子络合剂和流延溶剂。

99. 发明申请

US20070063392A1 MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT 有权
标题翻译：具有可移除边缘延伸元件的微电子基板
公开(公告)号：US20070063392A1
公开(公告)日：2007-03-22
申请号：US11162765
申请日：2005-09-22
申请人： Charles Koburger III , Steven Holmes , David Horak , Kurt Kimmel , Karen Petrillo , Christopher Robinson
发明人： Charles Koburger III , Steven Holmes , David Horak , Kurt Kimmel , Karen Petrillo , Christopher Robinson
IPC分类号： B29C35/08
CPC分类号： G03F7/70691 , G03F7/70341 , G03F7/70808
摘要： An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.
摘要翻译：提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。这种物品包括具有前表面，与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。前表面是物品的主要表面。具有前表面，后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。以这种方式，形成连续表面，其包括边缘延伸元件的前表面和微电子基底的前表面，连续表面基本上共平面且平坦，其中周缘连接到内边缘。

100. 发明授权

US08300452B2 Structure and method for improving storage latch susceptibility to single event upsets 有权
标题翻译：用于改善单个事件扰乱的存储锁存敏感性的结构和方法
公开(公告)号：US08300452B2
公开(公告)日：2012-10-30
申请号：US13050052
申请日：2011-03-17
申请人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
发明人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
IPC分类号： G11C11/00
CPC分类号： H01L27/11 , G11C11/4125 , H01L27/0921 , H01L27/1104 , H01L29/66181 , H03K3/0375
摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).
摘要翻译：数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

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