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91. 发明授权

US06825102B1 Method of improving the quality of defective semiconductor material 失效
标题翻译：提高缺陷半导体材料质量的方法
公开(公告)号：US06825102B1
公开(公告)日：2004-11-30
申请号：US10664714
申请日：2003-09-18
申请人： Stephen W. Bedell , Keith E. Fogel , Shreesh Narasimha , Devendra K. Sadana
发明人： Stephen W. Bedell , Keith E. Fogel , Shreesh Narasimha , Devendra K. Sadana
IPC分类号： H01L21263
CPC分类号： H01L21/02667 , H01L21/02529 , H01L21/02532 , H01L21/02538 , H01L21/2022 , Y10S438/933
摘要： A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.
摘要翻译：提供一种方法，其中对缺陷半导体晶体材料进行非晶化步骤之后进行热处理步骤。非晶化步骤使部分地或完全地形成缺陷半导体晶体材料的区域，包括表面区域。接下来进行热处理步骤，以便使缺陷半导体晶体材料的非晶化区域再结晶。通过从缺陷半导体晶体材料的非非晶化区域的固相晶体再生长，在本发明中实现了重结晶。

92. 发明申请

US20130269860A1 TEMPERATURE-CONTROLLED DEPTH OF RELEASE LAYER 审中-公开
标题翻译：释放层的温度控制深度
公开(公告)号：US20130269860A1
公开(公告)日：2013-10-17
申请号：US13448939
申请日：2012-04-17
申请人： Maha M. Khayyat , Norma E. Sosa Cortes , Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana
发明人： Maha M. Khayyat , Norma E. Sosa Cortes , Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana
IPC分类号： B32B38/00 , B05D3/02
CPC分类号： B32B38/10 , B32B2457/14 , H01L21/02002 , H01L21/304 , H01L21/6836 , H01L31/1892 , Y02E10/50
摘要： A stressor layer is formed atop a base substrate at a first temperature which induces a first tensile stress in the base substrate that is below a fracture toughness of base substrate. The base substrate and the stressor layer are then brought to a second temperature which is less than the first temperature. The second temperature induces a second tensile stress in the stressor layer which is greater than the first tensile stress and which is sufficient to allow for spalling mode fracture to occur within the base substrate. The base substrate is spalled at the second temperature to form a spalled material layer. Spalling occurs at a fracture depth which is dependent upon the fracture toughness of the base substrate, stress level within the base substrate, and the second tensile stress of the stressor layer induced at the second temperature.
摘要翻译：在第一温度下在基底顶部形成应力层，该第一温度在基础基板中引起低于基底基板的断裂韧性的第一拉伸应力。然后使基底和应力层达到小于第一温度的第二温度。第二温度在应力层中引起第二拉伸应力，其大于第一拉伸应力，并且其足以允许在基底基底内发生剥落模式断裂。基底基板在第二温度下剥离以形成剥离的材料层。剥离发生在取决于基底的断裂韧性，基底衬底内的应力水平以及在第二温度下引起的应力层的第二拉伸应力的断裂深度。

93. 发明授权

US07507988B2 Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer 失效
标题翻译：包括基本上松弛的低缺陷密度SiGe层的半导体异质结构
公开(公告)号：US07507988B2
公开(公告)日：2009-03-24
申请号：US11619040
申请日：2007-01-02
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L29/06
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of from about 50 to about 80% and a defect density of less than about 108 defects/cm2. A strained epitaxial Si layer is located atop the substantially relaxed SiGe layer and at least one alternating stack including a bottom relaxed SiGe layer and an top strained Si layer located on the strained epitaxial Si layer.
摘要翻译：提供了异质结构，其包括位于衬底上的绝缘区域上的基本上松弛的SiGe层。基本上松弛的SiGe层具有约2000nm或更小的厚度，约50至约80％的测量晶格弛豫和小于约108缺陷/ cm 2的缺陷密度。应变外延Si层位于基本上松弛的SiGe层之上，并且至少一个交替堆叠包括位于应变外延Si层上的底部松弛SiGe层和顶部应变Si层。

94. 发明授权

US07358166B2 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US07358166B2
公开(公告)日：2008-04-15
申请号：US11208359
申请日：2005-08-19
申请人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L21/205 , H01L21/477
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

95. 发明授权

US07348253B2 High-quality SGOI by annealing near the alloy melting point 有权
标题翻译：高品质SGOI通过在合金熔点附近退火
公开(公告)号：US07348253B2
公开(公告)日：2008-03-25
申请号：US10855915
申请日：2004-05-27
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
IPC分类号： H01L21/84
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

96. 发明授权

US07172930B2 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer 有权
标题翻译：通过掩埋的p +硅锗层的阳极氧化应变的绝缘体上硅
公开(公告)号：US07172930B2
公开(公告)日：2007-02-06
申请号：US10883887
申请日：2004-07-02
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L21/00 , H01L21/84 , H01L21/331 , H01L21/8222 , H01L21/36
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

97. 发明授权

US07141115B2 Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers 有权
标题翻译：使用不含锗含锗源层制造绝缘体上硅材料的方法
公开(公告)号：US07141115B2
公开(公告)日：2006-11-28
申请号：US10932598
申请日：2004-09-02
申请人： Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana
IPC分类号： C30B25/12
CPC分类号： H01L21/76254
摘要： A method of fabricating a high-quality relaxed SiGe-on-insulator substrate material is provided in which a prefabricated silicon-on-insulator substrate is first exposed to an unstrained Ge-containing source and then heated (annealed/oxidized) to cause Ge diffusion and thermal mixing of Ge within a single-crystal Si-containing layer of the prefabricated silicon-on-insulator substrate. The unstrained Ge-containing source can comprise a solid Ge-containing source, a gaseous Ge-containing source, or ions of Ge.
摘要翻译：提供一种制造高质量松散的绝缘体上硅衬底材料的方法，其中首先将预制的绝缘体上硅衬底暴露于未应变的含Ge源，然后加热（退火/氧化）以引起Ge扩散以及在预制的绝缘体上硅衬底的单晶含硅层内的Ge的热混合。不含锗的含锗源可以包含固体含Ge源，含Ge气体源或Ge离子。

98. 发明授权

US07125458B2 Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer 失效
标题翻译：通过掩埋多孔硅层的氧化形成绝缘体上硅结构的结构
公开(公告)号：US07125458B2
公开(公告)日：2006-10-24
申请号：US10662028
申请日：2003-09-12
申请人： Stephen W. Bedell , Kwang Su Choe , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Kwang Su Choe , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L21/20
CPC分类号： H01L21/76227 , C22F1/10 , H01L21/02378 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02667 , H01L21/76245 , H01L29/78603
摘要： A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.
摘要翻译：提供一种形成依赖于在含Ge层下形成的多孔硅层（或区域）的氧化的绝缘体上硅的简单且直接的方法。该方法包括以下步骤：提供包括其中形成有富空穴的含Si衬底和含Si衬底顶部的含Ge层的结构; 将富含孔的区域转化为多孔区域; 并退火包括多孔区域的结构，以提供基本上松弛的绝缘体上的SiGe。

99. 发明授权

US06805962B2 Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications 有权
标题翻译：为应变Si CMOS应用创造高品质松弛SiGe绝缘体的方法
公开(公告)号：US06805962B2
公开(公告)日：2004-10-19
申请号：US10055138
申请日：2002-01-23
申请人： Stephen W. Bedell , Jack O. Chu , Keith E. Fogel , Steven J. Koester , Devendra K. Sadana , John Albrecht Ott
发明人： Stephen W. Bedell , Jack O. Chu , Keith E. Fogel , Steven J. Koester , Devendra K. Sadana , John Albrecht Ott
IPC分类号： B32B900
CPC分类号： H01L21/76243 , H01L21/02378 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02612 , H01L21/2251 , H01L21/324 , H01L27/1203 , H01L29/66916 , Y10S438/938 , Y10T428/12674 , Y10T428/265 , Y10T428/31848
摘要： A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diffusion of Ge. Optionally forming a Si cap layer over the SiGe or pure Ge layer, and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer, the optional Si cap and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate materials are also disclosed herein.
摘要翻译：提供一种形成薄的，高质量的松散的绝缘体上硅衬底材料的方法，其首先包括在第一单晶Si层的表面上形成SiGe或纯Ge层，该第一单晶Si层存在于阻挡层上对Ge的扩散。可选择地在SiGe或纯Ge层上形成Si覆盖层，然后在允许Ge遍及第一单晶Si层的相互扩散的温度下加热各层，任选的Si盖和SiGe或纯Ge层，从而形成基本上松弛的单晶SiGe层在阻挡层顶上。附加的SiGe再生长和/或应变外延层的形成可以遵循上述步骤。绝缘体上硅衬底材料以及至少包括绝缘体上硅衬底材料的结构也在本文中公开。

100. 发明授权

US08933456B2 Germanium-containing release layer for transfer of a silicon layer to a substrate 有权
标题翻译：含锗释放层，用于将硅层转移到基底
公开(公告)号：US08933456B2
公开(公告)日：2015-01-13
申请号：US13616322
申请日：2012-09-14
申请人： Stephen W. Bedell , Keith E. Fogel , Daniel A. Inns , Jeehwan Kim , Devendra K. Sadana , Katherine L. Saenger
发明人： Stephen W. Bedell , Keith E. Fogel , Daniel A. Inns , Jeehwan Kim , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L29/38 , H01L21/02 , H01L21/762
CPC分类号： H01L21/0262 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02664 , H01L21/76254
摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.
摘要翻译：含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。任选地，可以在含锗层上生长或替代含锗层。随后将至少部分结晶的硅层沉积在含锗层上。手柄基板结合到至少部分结晶的硅层。本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅层。去除复合衬底上任何剩余的含锗层。

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