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91. 发明授权

US06179709B2 In-situ monitoring of linear substrate polishing operations 失效
标题翻译：线性衬底抛光操作的原位监控
公开(公告)号：US06179709B2
公开(公告)日：2001-01-30
申请号：US09244816
申请日：1999-02-04
申请人： Fred C. Redeker , Manoocher Birang , Shijian Li , Sasson Somekh
发明人： Fred C. Redeker , Manoocher Birang , Shijian Li , Sasson Somekh
IPC分类号： B24B100
CPC分类号： B24B37/005 , B24B21/04 , B24B49/04 , B24B49/12 , H01L21/30625
摘要： A substrate polishing scheme (apparatus and method) is described according to which a polishing surface of a polishing sheet is driven in a generally linear direction by a drive mechanism, a surface of a substrate is held against the polishing surface of the polishing sheet by a polishing head, and the substrate is probed through the polishing sheet by a monitoring system.
摘要翻译：描述了基板抛光方案（装置和方法），根据该基板抛光方案，研磨片的抛光表面通过驱动机构在大致线性方向上被驱动，基板的表面通过一个抛光头，并且通过监视系统通过抛光片探测基板。

92. 发明授权

US08519461B2 Device with post-contact back end of line through-hole via integration 有权
标题翻译：具有后触点后端的器件通过集成的通孔通孔
公开(公告)号：US08519461B2
公开(公告)日：2013-08-27
申请号：US13455453
申请日：2012-04-25
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/02
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了三维集成电路的器件结构和方法，该三维集成电路包括用于三维集成电路的集成的线通孔的后接后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

93. 发明申请

US20120024230A1 APPARATUSES AND SYSTEMS FOR FABRICATING THREE DIMENSIONAL INTEGRATED CIRCUITS 审中-公开
标题翻译：制作三维集成电路的装置和系统
公开(公告)号：US20120024230A1
公开(公告)日：2012-02-02
申请号：US13253829
申请日：2011-10-05
申请人： Shijian Li , Fritz Redeker , Yezdi Dordi
发明人： Shijian Li , Fritz Redeker , Yezdi Dordi
IPC分类号： H01L21/70 , B25B11/00 , C23C16/50 , C23C16/44 , C23C16/458
CPC分类号： H01L21/70 , C23C16/045 , C23C16/4586 , H01L21/67017 , H01L21/677 , H01L21/6838 , H01L21/68714 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , Y10T24/44 , H01L2924/00012 , H01L2924/00
摘要： The present invention pertains to methods, apparatuses, and systems for fabricating three-dimensional integrated circuits. One or more embodiments of systems, apparatuses, and/or methods according to the present invention are presented.
摘要翻译：本发明涉及用于制造三维集成电路的方法，装置和系统。呈现了根据本发明的系统，装置和/或方法的一个或多个实施例。

94. 发明授权

US07980255B2 Single wafer dryer and drying methods 有权
标题翻译：单片干燥机和干燥方法
公开(公告)号：US07980255B2
公开(公告)日：2011-07-19
申请号：US11846400
申请日：2007-08-28
申请人： Younes Achkire , Alexander Lerner , Boris T. Govzman , Boris Fishkin , Michael Sugarman , Rashid Mavleiv , Haoquan Fang , Shijian Li , Guy Shirazi , Jianshe Tang
发明人： Younes Achkire , Alexander Lerner , Boris T. Govzman , Boris Fishkin , Michael Sugarman , Rashid Mavleiv , Haoquan Fang , Shijian Li , Guy Shirazi , Jianshe Tang
IPC分类号： B08B3/04
CPC分类号： H01L21/67034 , B08B3/10 , H01L21/67751 , H01L21/681 , H01L21/68764 , Y10S414/139
摘要： In a first aspect, a module is provided that is adapted to process a wafer. The module includes a processing portion having one or more features such as (1) a rotatable wafer support for rotating an input wafer from a first orientation wherein the wafer is in line with a load port to a second orientation wherein the wafer is in line with an unload port; (2) a catcher adapted to contact and travel passively with a wafer as it is unloaded from the processing portion; (3) an enclosed output portion adapted to create a laminar air flow from one side thereof to the other; (4) an output portion having a plurality of wafer receivers; (5) submerged fluidnozzles; and/or (6) drying gas flow deflectors, etc. Other aspects include methods of wafer processing.
摘要翻译：在第一方面，提供一种适于处理晶片的模块。模块包括具有一个或多个特征的处理部分，例如（1）可旋转晶片支撑件，用于从第一取向旋转输入晶片，其中晶片与负载端口对准至第二取向，其中晶片与卸货港（2）捕捉器，其适于在从所述处理部分卸载时与晶片被动接触和行进; （3）适于产生从其一侧到另一侧的层流空气流的封闭输出部分; （4）具有多个晶片接收器的输出部分; （5）浸没液体喷嘴; 和/或（6）干燥气体导流板等。其它方面包括晶片处理的方法。

95. 发明授权

US07968439B2 Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces 有权
标题翻译：等离子体浸没离子注入方法，在室内表面上使用纯的或接近纯的硅调味层
公开(公告)号：US07968439B2
公开(公告)日：2011-06-28
申请号：US12069424
申请日：2008-02-06
申请人： Shijian Li , Kartik Ramaswamy , Hiroji Hanawa , Seon-Mee Cho , Biagio Gallo , Dongwon Choi , Majeed A. Foad
发明人： Shijian Li , Kartik Ramaswamy , Hiroji Hanawa , Seon-Mee Cho , Biagio Gallo , Dongwon Choi , Majeed A. Foad
IPC分类号： H01L21/425
CPC分类号： H01J37/32412 , C23C14/48 , C23C14/564 , H01L21/2236
摘要： Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction.
摘要翻译：在静电卡盘上采用非常高的RF偏置电压以获得必要的植入深度分布的等离子体浸没离子注入是通过在晶片引入之前首先在内部腔室表面上沉积部分导电的含硅调节层来进行的。

96. 发明申请

US20100267229A1 METHODS AND SYSTEMS FOR LOW INTERFACIAL OXIDE CONTACT BETWEEN BARRIER AND COPPER METALLIZATION 有权
标题翻译：阻挡层和铜金属之间的低界面氧化物接触的方法和系统
公开(公告)号：US20100267229A1
公开(公告)日：2010-10-21
申请号：US12828082
申请日：2010-06-30
申请人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/768
CPC分类号： C25D7/123 , C23C18/1653 , C23C28/023 , C23C28/322 , C23C28/34 , C23C28/341 , H01L21/28562 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于半导体器件金属化的方法和系统。本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。该方法还包括在ALD铜上沉积间隙填充铜层。本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。在一个实施例中，集成系统包括至少一个阻挡层沉积模块。该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

97. 发明申请

US20100006124A1 SINGLE WAFER DRYER AND DRYING METHODS 审中-公开
标题翻译：单辊干燥机和干燥方法
公开(公告)号：US20100006124A1
公开(公告)日：2010-01-14
申请号：US12345605
申请日：2008-12-29
申请人： Younes Achkire , Alexander Lerner , Boris T. Govzman , Boris Fishkin , Michael Sugarman , Rashid Mavleiv , Hoaquan Fang , Shijian Li , Guy Shirazi , Jianshe Tang
发明人： Younes Achkire , Alexander Lerner , Boris T. Govzman , Boris Fishkin , Michael Sugarman , Rashid Mavleiv , Hoaquan Fang , Shijian Li , Guy Shirazi , Jianshe Tang
IPC分类号： B08B5/00
CPC分类号： H01L21/67034 , B08B3/10 , H01L21/67751 , H01L21/681 , H01L21/68764 , Y10S414/139
摘要： In a first aspect, a module is provided that is adapted to process a wafer. The module includes a processing portion having one or more features such as (1) a rotatable wafer support for rotating an input wafer from a first orientation wherein the wafer is in line with a load port to a second orientation wherein the wafer is in line with an unload port; (2) a catcher adapted to contact and travel passively with a wafer as it is unloaded from the processing portion; (3) an enclosed output portion adapted to create a laminar air flow from one side thereof to the other; (4) an output portion having a plurality of wafer receivers; (5) submerged fluid nozzles; and/or (6) drying gas flow deflectors, etc. Other aspects include methods of wafer processing.
摘要翻译：在第一方面，提供一种适于处理晶片的模块。模块包括具有一个或多个特征的处理部分，例如（1）可旋转晶片支撑件，用于从第一取向旋转输入晶片，其中晶片与负载端口对准至第二取向，其中晶片与卸货港（2）捕捉器，其适于在从所述处理部分卸载时与晶片被动接触和行进; （3）适于产生从其一侧到另一侧的层流空气流的封闭输出部分; （4）具有多个晶片接收器的输出部分; （5）浸没式流体喷嘴; 和/或（6）干燥气体导流板等。其它方面包括晶片处理的方法。

98. 发明授权

US07615480B2 Methods of post-contact back end of the line through-hole via integration 有权
标题翻译：线后通孔的通孔整合方法
公开(公告)号：US07615480B2
公开(公告)日：2009-11-10
申请号：US11820811
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/20
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。在一个实施例中，该方法包括通过硬掩模和前金属电介质形成金属插头触点到半导体中的晶体管。该方法还包括使用图案化的光致抗蚀剂工艺将用于通孔的通孔穿过硬掩模蚀刻到半导体，去除图案化的光致抗蚀剂并使用硬掩模工艺将孔蚀刻到半导体中的量。所述方法还包括沉积介电衬垫以将所述孔与所述半导体隔离，沉积间隙填充金属以填充所述孔，以及将所述衬底的表面平面化至所述硬掩模。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

99. 发明申请

US20090233384A1 METHOD FOR MEASURING DOPANT CONCENTRATION DURING PLASMA ION IMPLANTATION 有权
标题翻译：在等离子体植入过程中测量痰浓度的方法
公开(公告)号：US20090233384A1
公开(公告)日：2009-09-17
申请号：US12049047
申请日：2008-03-14
申请人： Majeed A. Foad , Shijian Li
发明人： Majeed A. Foad , Shijian Li
IPC分类号： H01L21/66
CPC分类号： G01N21/68 , G01N21/59 , H01L21/26513 , H01L22/12 , H01L22/26
摘要： Embodiments of the invention generally provide methods for end point detection at predetermined dopant concentrations during plasma doping processes. In one embodiment, a method includes positioning a substrate within a process chamber, generating a plasma above the substrate and transmitting a light generated by the plasma through the substrate, wherein the light enters the topside and exits the backside of the substrate, and receiving the light by a sensor positioned below the substrate. The method further provides generating a signal proportional to the light received by the sensor, implanting the substrate with a dopant during a doping process, generating multiple light signals proportional to a decreasing amount of the light received by the sensor during the doping process, generating an end point signal proportional to the light received by the sensor once the substrate has a final dopant concentration, and ceasing the doping process.
摘要翻译：本发明的实施方案通常提供了在等离子体掺杂过程期间以预定掺杂剂浓度进行终点检测的方法。在一个实施例中，一种方法包括将衬底定位在处理室内，在衬底上方产生等离子体，并将由等离子体产生的光透射穿过衬底，其中光进入顶侧并离开衬底的背面，并接收通过位于基板下方的传感器进行光照射。该方法进一步提供产生与传感器接收的光成比例的信号，在掺杂过程期间用掺杂剂注入衬底，在掺杂过程期间产生与传感器接收的减少量的光成比例的多个光信号，产生一旦衬底具有最终的掺杂剂浓度，终点信号与传感器接收的光成比例，并停止掺杂过程。

100. 发明申请

US20090197401A1 Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces 有权
标题翻译：等离子体浸没离子注入方法，在室内表面上使用纯的或接近纯的硅调味层
公开(公告)号：US20090197401A1
公开(公告)日：2009-08-06
申请号：US12069424
申请日：2008-02-06
申请人： Shijian Li , Kartik Ramaswamy , Hiroji Hanawa , Seon-Mee Cho , Biagio Gallo , Dongwon Choi , Majeed A. Foad
发明人： Shijian Li , Kartik Ramaswamy , Hiroji Hanawa , Seon-Mee Cho , Biagio Gallo , Dongwon Choi , Majeed A. Foad
IPC分类号： H01L21/26
CPC分类号： H01J37/32412 , C23C14/48 , C23C14/564 , H01L21/2236
摘要： Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction.
摘要翻译：在静电卡盘上采用非常高的RF偏置电压以获得必要的植入深度分布的等离子体浸没离子注入是通过在晶片引入之前首先在内部腔室表面上沉积部分导电的含硅调节层来进行的。

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