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91. 发明授权

US06194310B1 Method of forming amorphous conducting diffusion barriers 有权
标题翻译：形成无定形导电扩散阻挡层的方法
公开(公告)号：US06194310B1
公开(公告)日：2001-02-27
申请号：US09585680
申请日：2000-06-01
申请人： Sheng Teng Hsu , Douglas James Tweet , Wei Pan , David Russell Evans
发明人： Sheng Teng Hsu , Douglas James Tweet , Wei Pan , David Russell Evans
IPC分类号： H01L214763
CPC分类号： H01L21/76864 , H01L21/28556 , H01L2221/1078
摘要： A method of forming conducting diffusion barriers is provided. The method produces substantially amorphous conducting diffusion barriers by depositing materials with varying ratios of elements throughout the diffusion barrier. Diffusion barriers of metal nitride, metal silicon nitride, are deposited using CVD, PECVD, or ALCVD, by depositing material with a first ratio of elements and then depositing substantially identical material with a different ratio of elements. The actual elements used are the same, but the ratio is changed. By changing the ratio of the elements within the same diffusion barrier, density variations are produced, and the material is not able to form undesirable polycrystalline structures.
摘要翻译：提供形成导电扩散阻挡层的方法。该方法通过在整个扩散阻挡层中沉积具有不同比例的元素的材料来产生基本上非晶的导电扩散阻挡层。使用CVD，PECVD或ALCVD沉积金属氮化物，金属氮化硅的扩散屏障，通过以第一比例的元素沉积材料，然后沉积具有不同比例元素的基本相同的材料。使用的实际元素是相同的，但是比例是改变的。通过改变相同扩散阻挡层内的元素的比例，产生密度变化，并且材料不能形成不期望的多晶结构。

92. 发明授权

US08264081B2 Multilayered barrier metal thin-films 有权
标题翻译：多层阻隔金属薄膜
公开(公告)号：US08264081B2
公开(公告)日：2012-09-11
申请号：US11311546
申请日：2005-12-19
申请人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.
摘要翻译：通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。整个多层膜的厚度可以是大约50埃。当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

93. 发明授权

US07192866B2 Source alternating MOCVD processes to deposit tungsten nitride thin films as barrier layers for MOCVD copper interconnects 失效
标题翻译：源交替MOCVD工艺沉积氮化钨薄膜作为MOCVD铜互连的阻挡层
公开(公告)号：US07192866B2
公开(公告)日：2007-03-20
申请号：US10326712
申请日：2002-12-19
申请人： Wei Pan , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28556 , H01L2221/1078
摘要： An alternating source MOCVD process is provided for depositing tungsten nitride thin films for use as barrier layers for copper interconnects. Alternating the tungsten precursor produces fine crystal grain films, or possibly amorphous films. The nitrogen source may also be alternated to form WN/W alternating layer films, as tungsten is deposited during periods where the nitrogen source is removed.
摘要翻译：提供了用于沉积用作铜互连的阻挡层的氮化钨薄膜的交替源MOCVD工艺。交替钨前体产生细晶粒膜或可能的非晶膜。氮源也可以交替形成WN / W交替层膜，因为在氮源被去除的时期期间钨被沉积。

94. 发明授权

US07015138B2 Multi-layered barrier metal thin films for Cu interconnect by ALCVD 有权
公开(公告)号：US07015138B2
公开(公告)日：2006-03-21
申请号：US09819296
申请日：2001-03-27
申请人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/44
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

95. 发明授权

US06777327B2 Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics 失效
标题翻译：在Cu沉积之前进行阻隔金属表面处理以提高粘附性和沟槽填充特性的方法
公开(公告)号：US06777327B2
公开(公告)日：2004-08-17
申请号：US09820068
申请日：2001-03-28
申请人： Wei Pan , Jer-Shen Maa , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Jer-Shen Maa , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , C23C16/0209 , C23C16/18 , H01L21/28556 , H01L21/76864 , H01L21/76876
摘要： A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables. Accordingly, the process disclosed herein is an enabling technology for the use of metal organic CVD (MOCVD) Cu in IC fabrication.
摘要翻译：快速热处理（RTP）提供了在沉积Cu膜之前预处理通过原位或原位CVD或物理气相沉积（PVD）预涂覆有阻挡金属膜的硅晶片的步骤在非反应性气体如氢气（H 2），氩气（Ar）或氦气（He））或在环境真空中，在250-550摄氏度的温度范围内。室压力通常在0.1mTorr和20Torr之间，并且RTP时间通常在30至100秒之间。在沉积Cu膜之前进行这种快速热处理会导致沉积在各种阻挡金属表面上的薄而有光泽，致密成核和粘附的Cu膜。预处理过程消除了由Cu前体引起的沉积的Cu膜的变化，并且对前体组成，挥发性和其它前体变量的变化不敏感。因此，本文公开的方法是在IC制造中使用金属有机CVD（MOCVD）Cu的使能技术。

96. 发明授权

US06716744B2 Ultra thin tungsten metal films used as adhesion promoter between barrier metals and copper 有权
标题翻译：超薄钨金属膜用作阻挡金属和铜之间的粘合促进剂
公开(公告)号：US06716744B2
公开(公告)日：2004-04-06
申请号：US10140460
申请日：2002-05-06
申请人： Wei Pan , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/28556 , H01L21/28562 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of adhering copper thin film to a substrate in an integrated circuit structure includes preparing a substrate, including forming active regions and trenches for interconnect structures; depositing a metal barrier layer on the substrate; depositing an ultra thin film layer of tungsten over the barrier metal layer; depositing a copper thin film on the tungsten ultra thin film layer; removing excess copper and tungsten to the level of the metal barrier layer; and completing the integrated circuit structure. An integrated circuit having a copper interconnect therein formed over a layer of barrier metal includes a substrate, including active regions, vias and trenches for interconnect structures; a metal barrier layer formed on the substrate, wherein said metal barrier layer is taken from the group of materials consisting of Ta, TiN, TaN, TaSiN and TiSiN, and formed to a thickness of between about 5 nm to 10 nm; an ultra thin film layer of tungsten formed on the barrier metal layer, said tungsten ultra thin film layer having a thickness of between about 1 nm to 5 nm; and a copper thin film layer formed on the tungsten ultra thin film layer to a thickness sufficient to fill the vias and trenches.
摘要翻译：在集成电路结构中将铜薄膜粘合到基板上的方法包括制备基板，包括形成用于互连结构的有源区和沟槽; 在衬底上沉积金属阻挡层; 在所述阻挡金属层上沉积钨的超薄膜层; 在钨超薄膜层上沉积铜薄膜; 将过量的铜和钨去除到金属阻挡层的水平; 并完成集成电路结构。在其上形成有铜互连的集成电路包括一个衬底，包括有源区，用于互连结构的通孔和沟槽; 形成在所述基板上的金属阻挡层，其中所述金属阻挡层取自由Ta，TiN，TaN，TaSiN和TiSiN组成的材料组，并形成为约5nm至10nm的厚度; 形成在所述阻挡金属层上的钨的超薄膜层，所述钨超薄膜层的厚度为约1nm至5nm; 以及形成在钨超薄膜层上的厚度足以填充通路和沟槽的厚度的铜薄膜层。

97. 发明授权

US06642138B2 Process of making dual damascene structures using a sacrificial polymer 失效
标题翻译：使用牺牲聚合物制造双镶嵌结构的工艺
公开(公告)号：US06642138B2
公开(公告)日：2003-11-04
申请号：US10112439
申请日：2002-03-29
申请人： Wei Pan , Sheng Teng Hsu
发明人： Wei Pan , Sheng Teng Hsu
IPC分类号： H01L218234
CPC分类号： H01L21/76811 , H01L21/76813 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method is provided to deposit and pattern a sacrificial polymer, and form metal layers. A double hard mask is used to pattern and etch the sacrificial polymer. The double hard mask may be formed at temperatures below 400° C. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.
摘要翻译：提供了沉积和图案化牺牲聚合物并形成金属层的方法。使用双重硬掩模来雕刻和蚀刻牺牲聚合物。双重硬掩模可以在低于400℃的温度下形成。牺牲聚合物能够在退火过程中分解成气隙。

98. 发明授权

US06475813B1 MOCVD and annealing processes for C-axis oriented ferroelectric thin films 有权
标题翻译： C轴取向铁电薄膜的MOCVD和退火工艺
公开(公告)号：US06475813B1
公开(公告)日：2002-11-05
申请号：US09929711
申请日：2001-08-13
申请人： Tingkai Li , Wei Pan , Sheng Teng Hsu
发明人： Tingkai Li , Wei Pan , Sheng Teng Hsu
IPC分类号： A01L2100
CPC分类号： H01L21/31691 , C23C16/40 , C30B25/02 , C30B29/30 , C30B29/32 , H01L21/31604
摘要： A method of fabricating a c-axis ferroelectric thin film includes preparing a substrate; depositing a layer of ferroelectric material by metal organic chemical vapor deposition, including using a precursor solution having a ferroelectric material concentration of about 0.1 M/L at a vaporizer temperature of between about 140° C. to 200° C.; and annealing the substrate and the ferroelectric material at a temperature between about 500° C. to 560° C. for between about 30 minutes to 120 minutes.
摘要翻译：制造c轴铁电薄膜的方法包括：制备基板; 通过金属有机化学气相沉积沉积铁电材料层，包括在蒸发器温度为约140℃至200℃之间使用铁电材料浓度为约0.1M / L的前体溶液; 以及在大约500℃至560℃之间的温度下将所述衬底和所述铁电材料退火约30分钟至120分钟。

99. 发明授权

US07905013B2 Method for forming an iridium oxide (IrOx) nanowire neural sensor array 有权
标题翻译：形成氧化铱（IrOx）纳米线神经传感器阵列的方法
公开(公告)号：US07905013B2
公开(公告)日：2011-03-15
申请号：US11809959
申请日：2007-06-04
申请人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
IPC分类号： H01K3/10
CPC分类号： A61N1/0543 , B82Y15/00 , B82Y30/00 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T428/24998
摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.
摘要翻译：提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

100. 发明授权

US07811913B2 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
标题翻译：制造低，暗电流硅 - 硅引脚光电探测器的方法
公开(公告)号：US07811913B2
公开(公告)日：2010-10-12
申请号：US11312967
申请日：2005-12-19
申请人： Jong-Jan Lee , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/265
CPC分类号： H01L31/105 , H01L31/1808 , H01L31/1864 , Y02E10/50 , Y02P70/521 , Y10S438/933
摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
摘要翻译：制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在硼掺杂的锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火来活化N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

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