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91. 发明授权

US6043164A Method for transferring a multi-level photoresist pattern 失效
标题翻译：转印多层光刻胶图案的方法
公开(公告)号：US6043164A
公开(公告)日：2000-03-28
申请号：US665014
申请日：1996-06-10
申请人： Tue Nguyen , Sheng Teng Hsu , Jer-shen Maa , Bruce Dale Ulrich , Chien-Hsiung Peng
发明人： Tue Nguyen , Sheng Teng Hsu , Jer-shen Maa , Bruce Dale Ulrich , Chien-Hsiung Peng
IPC分类号： G03F7/36 , H01L21/027 , H01L21/033 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76813 , H01L21/0274 , H01L21/0334 , H01L2221/1021
摘要： A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation.
摘要翻译：提供一种用于在使用具有中间厚度的光致抗蚀剂掩模的镶嵌工艺期间在集成电路电介质中形成中间电平的方法。该方法通过光致抗蚀剂图案中的开口形成到电介质中的第一深度的互连。光致抗蚀剂轮廓在中间厚度的区域被部分地蚀刻掉以露出第二电介质表面积。然后将第二电介质表面积蚀刻到小于第一深度的第二深度。以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。本发明的方法允许通过单步形成光致抗蚀剂来进行双镶嵌工艺。

92. 发明申请

US20080166878A1 Silicon nanostructures and fabrication thereof 审中-公开
标题翻译：硅纳米结构及其制造
公开(公告)号：US20080166878A1
公开(公告)日：2008-07-10
申请号：US11651242
申请日：2007-01-08
申请人： Tingkai Li , Bruce D. Ulrich , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/306
CPC分类号： H01L21/31111 , B81C1/00111 , H01L21/3065 , H01L21/31122
摘要： A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure elements; and dry etching, in one or more steps, the silicon wafer using the oxide hardmask to form a desired nanostructure having substantially parallel vertical sidewalls thereon.
摘要翻译：制造硅纳米结构的方法包括制备硅晶片作为基底; 在硅衬底上直接形成氧化层硬掩模; 图案化和蚀刻氧化物硬掩模; 湿蚀刻硅晶片以除去氧化物以减小氧化物硬掩模的尺寸并形成纳米结构元件; 以及使用氧化物硬掩模在一个或多个步骤中干蚀刻硅晶片以形成其上具有基本上平行的垂直侧壁的所需纳米结构。

93. 发明授权

US06777327B2 Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics 失效
标题翻译：在Cu沉积之前进行阻隔金属表面处理以提高粘附性和沟槽填充特性的方法
公开(公告)号：US06777327B2
公开(公告)日：2004-08-17
申请号：US09820068
申请日：2001-03-28
申请人： Wei Pan , Jer-Shen Maa , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Jer-Shen Maa , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , C23C16/0209 , C23C16/18 , H01L21/28556 , H01L21/76864 , H01L21/76876
摘要： A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables. Accordingly, the process disclosed herein is an enabling technology for the use of metal organic CVD (MOCVD) Cu in IC fabrication.
摘要翻译：快速热处理（RTP）提供了在沉积Cu膜之前预处理通过原位或原位CVD或物理气相沉积（PVD）预涂覆有阻挡金属膜的硅晶片的步骤在非反应性气体如氢气（H 2），氩气（Ar）或氦气（He））或在环境真空中，在250-550摄氏度的温度范围内。室压力通常在0.1mTorr和20Torr之间，并且RTP时间通常在30至100秒之间。在沉积Cu膜之前进行这种快速热处理会导致沉积在各种阻挡金属表面上的薄而有光泽，致密成核和粘附的Cu膜。预处理过程消除了由Cu前体引起的沉积的Cu膜的变化，并且对前体组成，挥发性和其它前体变量的变化不敏感。因此，本文公开的方法是在IC制造中使用金属有机CVD（MOCVD）Cu的使能技术。

94. 发明授权

US06555456B2 Method of forming iridium conductive electrode/barrier structure 失效
公开(公告)号：US06555456B2
公开(公告)日：2003-04-29
申请号：US10037192
申请日：2001-11-09
申请人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
发明人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/456 , H01L21/28291 , H01L28/55 , H01L28/65
摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

95. 发明授权

US06541385B2 Method for plasma etching of Ir-Ta-O electrode and for post-etch cleaning 失效
公开(公告)号：US06541385B2
公开(公告)日：2003-04-01
申请号：US09855393
申请日：2001-05-14
申请人： Hong Ying , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
发明人： Hong Ying , Fengyan Zhang , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21302
CPC分类号： H01L21/02071 , C04B41/009 , C04B41/5346 , C04B41/91 , C04B2111/00844 , H01L21/32136 , H01L28/60 , C04B35/495
摘要： A method of forming an electrode in an integrated circuit includes preparing a silicon-base substrate, including forming semiconductor structures on the substrate to form an integrated substrate structure; depositing a layer of electrode material on a substrate structure; patterning the layer of electrode material to form electrode elements, wherein said patterning includes plasma etching the layer of electrode material in a plasma reactor in an etching gas atmosphere having a fluorine component therein; and cleaning the substrate structure and electrode elements in a distilled water bath.

96. 发明授权

US06506637B2 Method to form thermally stable nickel germanosilicide on SiGe 失效
公开(公告)号：US06506637B2
公开(公告)日：2003-01-14
申请号：US09834488
申请日：2001-04-12
申请人： Jer-shen Maa , Douglas James Tweet , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas James Tweet , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/28525 , H01L21/28518 , H01L29/45
摘要： A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.

97. 发明授权

US6071782A Partial silicidation method to form shallow source/drain junctions 失效
标题翻译：部分硅化法形成浅源极/漏极结
公开(公告)号：US6071782A
公开(公告)日：2000-06-06
申请号：US23383
申请日：1998-02-13
申请人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
发明人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L29/78 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L21/28052 , H01L29/6659
摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.
摘要翻译：提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。首先，低温退火开始跨越源/漏电极表面的盐析过程。控制时间和温度，使得金属仅被部分消耗。中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。然后，在较高温度的退火下完成硅化。由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

98. 发明授权

US6048740A Ferroelectric nonvolatile transistor and method of making same 有权
标题翻译：铁电非易失性晶体管及其制造方法
公开(公告)号：US6048740A
公开(公告)日：2000-04-11
申请号：US187238
申请日：1998-11-05
申请人： Sheng Teng Hsu , Jer-shen Maa , Fengyang Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Jer-shen Maa , Fengyang Zhang , Tingkai Li
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/6684 , H01L29/78391
摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta., wherein .delta. is the alignment tolerance of the lithographic process.
摘要翻译：使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p-阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对结构进行金属化。铁电存储晶体管包括其中形成有p-阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ，其中Δ是光刻工艺的对准公差。

99. 发明授权

US5989965A Nitride overhang structures for the silicidation of transistor electrodes with shallow junction 失效
标题翻译：氮化硅突出结构用于具有浅结的晶体管电极的硅化
公开(公告)号：US5989965A
公开(公告)日：1999-11-23
申请号：US23032
申请日：1998-02-13
申请人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
发明人： Jer-Shen Maa , Sheng Teng Hsu , Chien-Hsiung Peng
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6656
摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.
摘要翻译：提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。还提供了通过上述方法制造的具有突出结构的晶体管。

100. 发明授权

US5814537A Method of forming transistor electrodes from directionally deposited silicide 失效
标题翻译：从定向沉积的硅化物形成晶体管电极的方法
公开(公告)号：US5814537A
公开(公告)日：1998-09-29
申请号：US768647
申请日：1996-12-18
申请人： Jer-shen Maa , Sheng Teng Hsu
发明人： Jer-shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/786 , H01L21/285
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L2924/0002 , Y10S148/147
摘要： A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed. Conductive lines, connecting to the electrodes across the field oxide, are fabricated from polycide, which includes a level of polysilicon covered with silicide, when the lower resistance surface of a metal-disilicide overlying the conductive line is required. The method of the present invention is applicable to bulk silicon, as well as SIMOX, transistor fabrication processes. An IC structure having different thicknesses of directionally deposited silicide, and a completed MOS transistor having interim thicknesses of directionally deposited silicide, are also provided.
摘要翻译：提供了一种用于在有源器件中的源极，漏极和栅电极上形成硅化物表面以降低电极表面的电阻而不消耗该工艺中的电极的硅的方法。硅化物被定向沉积在电极上，使得更大的厚度积聚在电极表面上，并且较小的厚度积聚在栅极侧壁表面上，隔离栅极与源极/漏极电极。然后，电极被各向同性地蚀刻，以便去除侧壁上较小的厚度，留下覆盖电极的至少一些厚度的硅化物。在其他步骤中，电极被光致抗蚀剂掩蔽，并且去除沉积在电极周围的场氧化物区域中的任何硅化物。当需要覆盖在导电线上的金属二硅化物的较低电阻表面时，由多晶硅半导体制造连接到场氧化物上的电极的导电线，其包括覆盖有硅化物的多晶硅层。本发明的方法可应用于体硅，以及SIMOX晶体管制造工艺。还提供了具有不同厚度的定向沉积的硅化物的IC结构和具有定向沉积的硅化物的中间厚度的完整的MOS晶体管。

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