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91. 发明申请

US20080253215A1 Semiconductor memory circuit 有权
标题翻译：半导体存储电路
公开(公告)号：US20080253215A1
公开(公告)日：2008-10-16
申请号：US11902877
申请日：2007-09-26
申请人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
发明人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译：本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。

92. 发明授权

US07427791B2 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
标题翻译：形成具有不同厚度的栅极绝缘膜的CMOS结构的方法
公开(公告)号：US07427791B2
公开(公告)日：2008-09-23
申请号：US11118951
申请日：2005-05-02
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L29/72
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
摘要翻译：半导体集成电路器件在相同的硅衬底上采用具有在源极和栅极之间或其漏极和栅极之间流动的不同大小的隧道电流的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。

93. 发明申请

US20080228414A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080228414A1
公开(公告)日：2008-09-18
申请号：US12122715
申请日：2008-05-18
申请人： Takayasu ITO , Mitsuru Hiraki , Masashi Horiguchi , Toyohiro Shimogawa
发明人： Takayasu ITO , Mitsuru Hiraki , Masashi Horiguchi , Toyohiro Shimogawa
IPC分类号： G06F19/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： The present invention provides a semiconductor device capable of realizing power saving and improvement in reliability or reduction in area. A semiconductor device includes: a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down; and an internal voltage determining circuit for determining voltage of the internal power supply in which power is shut down. Voltage of the internal power supply in which power is shut down is generated from voltage of an external power supply by using a regulator circuit. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When the power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, the increased voltage of the internal power supply is determined by the internal voltage determining circuit, operation of a circuit block is started, and the switch is turned on.
摘要翻译：本发明提供一种半导体装置，其能够实现节电，提高可靠性或减小面积。一种半导体装置，包括：连接不断电的内部电源的电源开关和断电的内部电源; 以及用于确定电源关闭的内部电源的电压的内部电压确定电路。通过使用调节电路从外部电源的电压产生关闭电源的内部电源的电压。当内部电源的电源中断时，电源开关关闭，调节器电路关闭，调节器电路的输出短路到地电位。当恢复内部电源的电源时，调节器电路接通，短路被取消，内部电源的增加的电压由内部电压确定电路确定，电路块的操作开始，开关打开

94. 发明授权

US07383138B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07383138B2
公开(公告)日：2008-06-03
申请号：US11401977
申请日：2006-04-12
申请人： Takayasu Ito , Mitsuru Hiraki , Masashi Horiguchi , Toyohiro Shimogawa
发明人： Takayasu Ito , Mitsuru Hiraki , Masashi Horiguchi , Toyohiro Shimogawa
IPC分类号： G01R21/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A semiconductor device includes: a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down; and an internal voltage determining circuit for determining voltage of the internal power supply in which power is shut down. Voltage of the internal power supply in which power is shut down is generated from external power supply voltage by using a regulator circuit. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, increased voltage of the internal power supply is determined, operation of a circuit block is started, and the switch is turned on.
摘要翻译：一种半导体装置，包括：连接不断电的内部电源的电源开关和断电的内部电源; 以及用于确定电源关闭的内部电源的电压的内部电压确定电路。通过使用调节器电路从外部电源电压产生关闭电源的内部电源的电压。当内部电源的电源中断时，电源开关关闭，调节器电路关闭，调节器电路的输出短路到地电位。当内部电源的电源恢复时，调节器电路接通，短路被取消，内部电源的电压升高，电路块的运行开始，开关导通。

95. 发明授权

US07345461B2 Semiconductor circuit device and data processing system 有权
公开(公告)号：US07345461B2
公开(公告)日：2008-03-18
申请号：US10940379
申请日：2004-09-14
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G05F1/40
CPC分类号： G05F3/242 , H01L2224/16145 , H01L2224/32245 , H01L2224/48137 , H01L2224/4826 , H01L2224/73215 , Y10T307/76 , H01L2924/00
摘要： Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises, and occurrence of noise is restrained.

96. 发明申请

US20070183226A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20070183226A1
公开(公告)日：2007-08-09
申请号：US11717080
申请日：2007-03-13
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C5/147 , H03K19/0013
摘要： A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

97. 发明授权

US07203101B2 Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US07203101B2
公开(公告)日：2007-04-10
申请号：US11330220
申请日：2006-01-12
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C7/10
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
摘要翻译：形成在半导体芯片上的半导体存储器件包括多个第一存储器阵列，多个第二存储器阵列，第一电压发生器和多个第一焊盘。半导体芯片被分成第一矩形区域，第二矩形区域和第三矩形区域，并且第三矩形区域布置在第一矩形区域和第二矩形区域之间。多个第一存储器阵列形成在第一矩形区域中。多个第二存储器阵列形成在第二矩形区域中。电压发生器和多个第一接合焊盘被布置在第三矩形区域中。多个第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和多个第二存储器阵列之间没有布置接合焊盘。

98. 发明授权

US07200054B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07200054B2
公开(公告)日：2007-04-03
申请号：US11156648
申请日：2005-06-21
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , H03K19/0013
摘要： A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
摘要翻译：提供了具有降低的消耗电流的半导体集成电路器件。第一降压电路固定地形成低于通过外部端子提供的电源电压的内部电压。根据控制信号，第二降压电路在第一模式和第二模式之间切换。在第一模式中，内部电压由通过外部端子提供的电源电压形成，并通过第二输出端子输出。在第二模式中，形成内部电压的控制系统的工作电流被中断，并且建立了输出高阻抗状态。第一降压电路的第一输出端子和第二降压电路的第二输出端子共同连接，并且内部电压被提供给内部电路。

99. 发明授权

US07082074B2 Semiconductor device having a power down mode 有权
公开(公告)号：US07082074B2
公开(公告)日：2006-07-25
申请号：US11183802
申请日：2005-07-19
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

100. 发明授权

US07072202B2 Semiconductor device having a power down mode 有权
标题翻译：具有掉电模式的半导体器件
公开(公告)号：US07072202B2
公开(公告)日：2006-07-04
申请号：US11084138
申请日：2005-03-21
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要翻译：提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。然而，第二电源电路在掉电模式期间连续运行。在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

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