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91. 发明授权

US06835656B1 Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon layer and in-situ anneal to reduce silicon consumption during salicidation 失效
标题翻译：在具有沉积硅层的半导体晶片中形成超浅结的方法和原位退火以减少在盐化期间的硅消耗
公开(公告)号：US06835656B1
公开(公告)日：2004-12-28
申请号：US10163459
申请日：2002-06-07
申请人： Paul R. Besser , Minh Van Ngo
发明人： Paul R. Besser , Minh Van Ngo
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/28525
摘要： A method for forming ultra-shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high-resistivity metal silicide regions are formed on the gate and source/drain junctions. Amorphous silicon is then deposited in a layer on the high resistivity metal silicide regions by high density plasma chemical vapor deposition. The deposition of the amorphous-silicon is at an elevated temperature which causes transforming of the high resistivity metal silicide regions to low resistivity metal silicide regions on the gate and source/drain junctions. The deposited amorphous-silicon acts as a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide to the low resistivity metal silicide.
摘要翻译：用于在半衰期期间形成超浅结的方法，其中在硅化过程中硅消耗减少，在盐析过程中提供额外的硅。在半导体器件中形成栅极和源极/漏极结之后，在栅极和源极/漏极结上形成高电阻金属硅化物区域。然后通过高密度等离子体化学气相沉积将非晶硅沉积在高电阻率金属硅化物区域的一层中。非晶硅的沉积处于升高的温度，这导致高电阻率金属硅化物区域转变为栅极和源极/漏极结上的低电阻率金属硅化物区域。沉积的非晶硅在高电阻率金属硅化物向低电阻率金属硅化物的转变期间充当硅源，用作扩散物质。

92. 发明授权

US06811448B1 Pre-cleaning for silicidation in an SMOS process 有权
标题翻译：在SMOS工艺中预硅化硅化
公开(公告)号：US06811448B1
公开(公告)日：2004-11-02
申请号：US10619879
申请日：2003-07-15
申请人： Eric N. Paton , Paul R. Besser , Qi Xiang
发明人： Eric N. Paton , Paul R. Besser , Qi Xiang
IPC分类号： H01L21302
CPC分类号： H01L21/02054 , H01L21/02046 , H01L21/02052 , H01L21/28518 , H01L29/665
摘要： A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用用于从晶片顶表面去除自然氧化物的协议。暴露于等离子体，例如含有氢气和氩气的等离子体可从顶表面除去天然氧化物，而不会引起过量的锗污染。该方案可以使用氟化氢浸渍。在使用等离子体之前可以使用氟化氢浸渍。该协议允许在SMOS器件中更好的硅化。

93. 发明授权

US06633085B1 Method of selectively alloying interconnect regions by ion implantation 有权
标题翻译：通过离子注入选择合金化互连区域的方法
公开(公告)号：US06633085B1
公开(公告)日：2003-10-14
申请号：US09884100
申请日：2001-06-20
申请人： Paul R. Besser , Larry Zhao , Donggang David Wu
发明人： Paul R. Besser , Larry Zhao , Donggang David Wu
IPC分类号： H01L2348
CPC分类号： H01L21/76814 , H01L21/76802 , H01L21/76825 , H01L21/76829 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metal interconnect structure and method of making the same implants ions of an alloy elements into a copper line through a via. Then ion implantation of the alloy elements in the copper line through the via provides improved electromigration properties at the copper line at a critical electromigration failure site, without attempting to provide alloy elements throughout the entire copper line.
摘要翻译：一种金属互连结构和方法，通过通孔将合金元素的离子注入铜线。然后通过通孔离子注入铜线中的合金元素，在临界电迁移破坏部位的铜线处提供了改善的电迁移特性，而不试图在整个铜线上提供合金元素。

94. 发明授权

US06602781B1 Metal silicide gate transistors 有权
标题翻译：金属硅化物晶体管
公开(公告)号：US06602781B1
公开(公告)日：2003-08-05
申请号：US09734207
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2144
CPC分类号： H01L21/28202 , H01L21/28097 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/66606 , H01L29/7833
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了金属在凹部中的部分之外，除去金属。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

95. 发明授权

US06555479B1 Method for forming openings for conductive interconnects 失效
标题翻译：用于形成导电互连的开口的方法
公开(公告)号：US06555479B1
公开(公告)日：2003-04-29
申请号：US09879376
申请日：2001-06-11
申请人： Frederick N. Hause , Paul R. Besser , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , John A. Iacoponi , Peter J. Beckage
发明人： Frederick N. Hause , Paul R. Besser , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , John A. Iacoponi , Peter J. Beckage
IPC分类号： H01L21302
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76813 , H01L2221/1021
摘要： A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. A conductive material is formed in the etched region in the process layer and any excess conductive material is removed from above an upper surface of the process layer.
摘要翻译：形成导电互连的方法包括在结构层上形成工艺层，并在工艺层上形成掩模，掩模在其中具有蚀刻轮廓。执行各向异性蚀刻处理以蚀刻掩模并在处理层中形成蚀刻区域，蚀刻区域具有与蚀刻轮廓相关的轮廓。在处理层的蚀刻区域中形成导电材料，并且从处理层的上表面上方除去任何过量的导电材料。

96. 发明授权

US06489240B1 Method for forming copper interconnects 失效
标题翻译：形成铜互连的方法
公开(公告)号：US06489240B1
公开(公告)日：2002-12-03
申请号：US09871305
申请日：2001-05-31
申请人： John A. Iacoponi , Paul R. Besser , Frederick N. Hause , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , Peter J. Beckage
发明人： John A. Iacoponi , Paul R. Besser , Frederick N. Hause , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , Peter J. Beckage
IPC分类号： H01L214763
CPC分类号： H01L21/76877 , H01L21/7684
摘要： A method for forming a semiconductor having improved copper interconnects is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the first dielectric layer and in the first opening. A portion of the first copper layer outside of the opening is removed. A surface portion of the first copper layer is also removed from within the opening, and a second layer of copper is formed above the first layer of copper, replacing the removed surface portion.
摘要翻译：提供了一种形成具有改进的铜互连的半导体的方法。该方法包括在第一结构层上形成第一电介质层。此后，在第一电介质层中形成第一开口，并且在第一电介质层上方和第一开口中形成第一铜层。除去开口外侧的第一铜层的一部分。第一铜层的表面部分也从开口内去除，并且在第一铜层之上形成第二铜层，代替去除的表面部分。

97. 发明授权

US06465349B1 Nitrogen-plasma treatment for reduced nickel silicide bridging 有权
标题翻译：氮等离子体处理用于还原硅化镍桥接
公开(公告)号：US06465349B1
公开(公告)日：2002-10-15
申请号：US09679372
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser , Robert A. Huertas
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/3115 , Y10S257/90
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译：通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面以形成具有减少的自由硅的表面区域，防止沿栅极电极的硅化镍层与氮化硅侧壁间隔物的源极/漏极区之间的桥接。实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

98. 发明授权

US06465309B1 Silicide gate transistors 有权
标题翻译：硅化物栅极晶体管
公开(公告)号：US06465309B1
公开(公告)日：2002-10-15
申请号：US09734185
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28097 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545
摘要： A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.
摘要翻译：半导体结构及其制造方法提供由氧氮化物形成的栅极电介质或形成在凹部内的氮化物/氧化物堆叠。非晶硅沉积在凹槽内的栅极电介质上，金属沉积在非晶硅上。退火工艺在栅极电介质的凹槽内形成金属硅化物栅极。可以选择更宽范围的金属材料，因为由氮氧化物或氮化物/氧化物堆叠形成的栅极电介质在硅化过程中保持稳定。金属硅化物栅极显着降低了栅极和栅极端子之间的薄层电阻。

99. 发明授权

US06455425B1 Selective deposition process for passivating top interface of damascene-type Cu interconnect lines 有权
标题翻译：选择性沉积工艺，用于钝化镶嵌型Cu互连线的顶部界面
公开(公告)号：US06455425B1
公开(公告)日：2002-09-24
申请号：US09484412
申请日：2000-01-18
申请人： Paul R. Besser , Darrell M. Erb , Sergey Lopatin
发明人： Paul R. Besser , Darrell M. Erb , Sergey Lopatin
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76867 , H01L21/76883 , H01L21/76886 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.
摘要翻译：通过包括选择性地在金属化特征的平坦化的上表面上沉积至少一个薄层的方法来增强平面化的在线金属化图案（例如铜）的可靠性，电迁移阻力，粘附性和电接触电阻，所述至少一个薄层包括用于所述特征金属的至少一种钝化元素，使所述至少一种钝化元素反应以化学还原存在于所述金属化特征的上表面处的任何有害的氧化物层，以及使所述至少一种钝化元件在所述上部表面形成钝化的顶部界面。钝化的顶部界面有利地表现出减少的电迁移和改善对具有较低的欧姆接触电阻的上覆金属化的附着。通过CMP，可以在反应/扩散之后进行平面化以除去至少一个薄层的任何升高的，反应的和/或未反应的部分。本发明特别适用于具有亚微米尺寸金属化特征的高密度集成电路半导体器件的“后端”金属化处理。

100. 发明授权

US06383906B1 Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption 有权
标题翻译：在具有超低硅消耗的半导体晶片中形成结漏电的金属硅化物的方法
公开(公告)号：US06383906B1
公开(公告)日：2002-05-07
申请号：US09641436
申请日：2000-08-18
申请人： Karsten Wieczorek , Nicholas Kepler , Paul R. Besser , Larry Y. Wang
发明人： Karsten Wieczorek , Nicholas Kepler , Paul R. Besser , Larry Y. Wang
IPC分类号： H01L214763
CPC分类号： H01L29/6653 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method for forming ultra shallow junctions in a semiconductor wafer uses disposable spacers and a silicon cap layer to achieve ultra-low low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of a semiconductor device. Silicon nitride disposable spacers are formed over the metal layer in the region of the sidewall spacers previously formed on the sidewalls of the gate. A silicon cap layer is deposited over the metal layer and the disposable spacers. Rapid thermal annealing is performed to form the high-ohmic phase of the salicide, with the disposable spacers preventing interaction and between the cobalt and the silicon in the area between the gate and the source/drain junctions along the sidewall spacers. The silicon cap layer provides a source of silicon for consumption during the first phase of salicide formation, reducing the amount of silicon of the source/drain junctions that is consumed.
摘要翻译：在半导体晶片中形成超浅结的方法使用一次性间隔物和硅帽层，以在自对准硅化物形成过程中实现超低的低硅消耗。难熔金属层，例如钴层，沉积在半导体器件的栅极和源极/漏极结上。氮化硅一次性间隔物形成在预先形成在栅极的侧壁上的侧壁间隔区域中的金属层的上方。在金属层和一次性间隔物上沉积硅覆盖层。进行快速热退火以形成硅化物的高欧姆相，其中一次性间隔物防止了沿着侧壁间隔物的栅极和源极/漏极结之间的区域中的钴和硅之间的相互作用。硅封层在硅化物形成的第一阶段期间提供硅消耗源，从而减少消耗的源极/漏极结的硅量。

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