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91. 发明授权

US07586281B2 Methods and apparatus for optimal voltage and frequency control of thermally limited systems 失效
标题翻译：用于最佳电压和频率控制的受热系统的方法和装置
公开(公告)号：US07586281B2
公开(公告)日：2009-09-08
申请号：US11459407
申请日：2006-07-24
申请人： Aviad Cohen , Lev Finkelstein , Avi Mendelson , Ronny Ronen , Dmitry Rudoy
发明人： Aviad Cohen , Lev Finkelstein , Avi Mendelson , Ronny Ronen , Dmitry Rudoy
IPC分类号： G05D23/00
CPC分类号： H02H6/005 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y10S388/934
摘要： Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.
摘要翻译：方法，装置和制品控制具有与操作速率或频率相关的操作限制的装置或系统。操作频率被控制为可变速率，其被计算为在足够长的计算时间段内最大化系统或设备性能，使得诸如功率消耗的控制因素在该时段期间不显着变化。使用已知的系统参数，例如集成电路（IC）及其封装的热阻和电容以及IC中的当前结温等测量值来计算即将到来的时间段的时间依赖性操作频率这导致最佳的整体性能，而不超过操作限制，如结温。

92. 发明授权

US07539850B2 Enhanced virtual renaming scheme and deadlock prevention therefor 失效
标题翻译：增强的虚拟重命名方案和防止死锁
公开(公告)号：US07539850B2
公开(公告)日：2009-05-26
申请号：US10351444
申请日：2003-01-27
申请人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
发明人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
IPC分类号： G06F9/34
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.
摘要翻译：在处理器内的增强型虚拟重命名方案中，可以将多个逻辑寄存器映射到单个物理寄存器。值缓存确定根据程序指令生成的新值是否与先前执行的指令相关联的值匹配。如果是，则与新执行的指令相关联的逻辑寄存器共享物理寄存器。此外，死锁预防措施可以以在处理器核心中产生来自旧指令的值产生时从较小执行指令“窃取”物理寄存器的方式集成到寄存器分配单元中。

93. 发明申请

US20070061021A1 Combining power prediction and optimal control approaches for performance optimization in thermally limited designs 有权
标题翻译：结合功率预测和优化控制方法进行热限制设计中的性能优化
公开(公告)号：US20070061021A1
公开(公告)日：2007-03-15
申请号：US11224568
申请日：2005-09-12
申请人： Aviad Cohen , Adam De La Zerda , Lev Finkelstein , Ronny Ronen , Dmitry Rudoy
发明人： Aviad Cohen , Adam De La Zerda , Lev Finkelstein , Ronny Ronen , Dmitry Rudoy
IPC分类号： G05B13/02 , G01M1/38
CPC分类号： G05B13/026
摘要： The operating rate of an electronic system is maximized without exceeding a thermal constraint, such as a maximum junction temperature of an integrated circuit (IC) or other portion of the electronic system. An operating parameter of the system that controls the thermal output of the system is calculated for an upcoming time period based upon the previously measured thermal performance relationship to the operating parameter level. If the predicted thermal performance will exceed a maximum allowable level of the thermal constraint, then the operating parameter is reduced by an amount calculated to keep the thermal constraint at a level just below the maximum allowable level, thus resulting in an optimal control approach to maximizing the system performance while not exceeding the thermal constraint.
摘要翻译：电子系统的运行速率最大化，而不超过热约束，例如集成电路（IC）或电子系统的其他部分的最大结温。基于先前测量的与操作参数水平的热性能关系，计算控制系统的热输出的系统的操作参数，用于即将到来的时间段。如果预测的热性能将超过热约束的最大允许水平，则将运行参数减少计算的量，以将热约束保持在刚好低于最大允许水平的水平，从而导致最佳化控制方法系统性能不超过热约束。

94. 发明申请

US20070050554A1 Power reduction for processor front-end by caching decoded instructions 失效
标题翻译：处理器前端通过缓存解码指令进行功耗降低
公开(公告)号：US20070050554A1
公开(公告)日：2007-03-01
申请号：US11589803
申请日：2006-10-31
申请人： Baruch Solomon , Ronny Ronen , Doron Orenstien
发明人： Baruch Solomon , Ronny Ronen , Doron Orenstien
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
摘要： A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
摘要翻译：用于处理器的功率感知前端单元可以包括禁用前端单元中的其他电路的UOP高速缓存。在一个实施例中，当块高速缓存和指令高速缓存中的指令查找正在进行时，前端单元可以禁用指令同步电路，指令解码电路和可选地的指令获取电路。如果指令查找表示未命中，则其后的禁用电路可以被使能。

95. 发明授权

US07155599B2 Method and apparatus for a register renaming structure 有权
标题翻译：一种寄存器重命名结构的方法和装置
公开(公告)号：US07155599B2
公开(公告)日：2006-12-26
申请号：US09750095
申请日：2000-12-29
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
IPC分类号： G06F9/40
CPC分类号： G06F9/384 , G06F9/3836 , G06F9/3857
摘要： A processor having a register renaming structure and method is disclosed to recover a free list. The processor includes a physical register file including physical registers. The processor also includes a decoder to decode an instruction to indicate a destination logical register. The processor also includes a register allocation table to map the destination logical register to an allocated physical register. The processor also includes an active list that includes an old field and a new field. The old field includes at least one evicted physical register from the register alias table. The new field includes the allocated physical register. The processor also includes the free list of unallocated physical registers reclaimed from the active list.
摘要翻译：公开了具有寄存器重命名结构和方法的处理器来恢复空闲列表。该处理器包括一个包括物理寄存器的物理寄存器文件。处理器还包括解码器，用于解码指示目的地逻辑寄存器的指令。处理器还包括寄存器分配表，以将目的地逻辑寄存器映射到所分配的物理寄存器。该处理器还包括一个包含旧字段和新字段的活动列表。旧字段至少包含一个从寄存器别名表中删除的物理寄存器。新的领域包括分配的物理寄存器。处理器还包括从活动列表中回收的未分配物理寄存器的空闲列表。

96. 发明授权

US07024542B2 System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions 失效
公开(公告)号：US07024542B2
公开(公告)日：2006-04-04
申请号：US10183096
申请日：2002-06-26
申请人： Guillermo Savransky , Ronny Ronen , Antonio Gonzalez
发明人： Guillermo Savransky , Ronny Ronen , Antonio Gonzalez
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A processor system and method that reduces the number of register value copying made from alias registers to corresponding real (architectural) registers. One method entails not performing an alias register to real register copying if the incoming instruction does not designate a real register. Another method entails delaying alias register to real register copying until the corresponding reorder buffer (ROB) entry is actually written to. Yet another method entails not performing an alias register to real register copying if the ROB entry is the same as the existing ROB entry. And, still another method entails further delaying or stalling the allocation of an ROB entry.

97. 发明授权

US07017026B2 Generating lookahead tracked register value based on arithmetic operation indication 失效
标题翻译：基于算术运算指示生成前瞻追踪寄存器值
公开(公告)号：US07017026B2
公开(公告)日：2006-03-21
申请号：US10848602
申请日：2004-05-18
申请人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
发明人： Adi Yoaz , Ronny Ronen , Stephan J. Jourdan , Michael Bekerman
IPC分类号： G06F9/34
CPC分类号： G06F9/30134 , G06F9/30167 , G06F9/383 , G06F9/3832 , G06F9/3842
摘要： Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.
摘要翻译：跟踪寄存器值的装置和方法。微处理器可以包括第一寄存器，控制电路和加法器。第一个寄存器可以存储跟踪的寄存器值。控制电路可以包括用于接收指令的至少一部分的指令输入和用于输出算术运算指示的第一输出。加法器可以包括用于接收算术运算指示的控制输入，用于接收指令的立即操作数的第一输入和用于接收所跟踪的寄存器值的第二输入。

98. 发明申请

US20050289529A1 Method and apparatus to vectorize multiple input instructions 有权
标题翻译：用于向多个输入指令进行矢量化的方法和装置
公开(公告)号：US20050289529A1
公开(公告)日：2005-12-29
申请号：US10874744
申请日：2004-06-24
申请人： Yoav Almog , Roni Rosner , Ronny Ronen
发明人： Yoav Almog , Roni Rosner , Ronny Ronen
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F9/3808 , G06F9/3885 , G06F9/3887
摘要： Briefly, an optimization unit to search for two or more candidate instructions in an instruction trace and to merge the two or more candidate instructions into a single instruction with multiple data (SIMD) according to a depth of a trace dependency and a common operation code of the two or more candidate instructions.
摘要翻译：简而言之，是优化单元，用于在指令轨迹中搜索两个或多个候选指令，并根据跟踪依赖性的深度和公用操作码将两个或多个候选指令合并成具有多个数据（SIMD）的单个指令两个或多个候选指令。

99. 发明授权

US06950928B2 Apparatus, method and system for fast register renaming using virtual renaming, including by using rename information or a renamed register 失效
标题翻译：使用虚拟重命名快速注册重命名的装置，方法和系统，包括使用重命名信息或重命名寄存器
公开(公告)号：US06950928B2
公开(公告)日：2005-09-27
申请号：US09822938
申请日：2001-03-30
申请人： Ronny Ronen , Adi Yoaz , Gregory Pribush
发明人： Ronny Ronen , Adi Yoaz , Gregory Pribush
IPC分类号： G06F9/38 , G06F9/50
CPC分类号： G06F9/3861 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method for renaming a source for use with a processor, the method including providing an instruction, building instruction dependency information based on the instruction, caching the instruction based on the instruction dependency information to provide a cached instruction, renaming a register based on the cached instruction to provide a renamed register, and multiplexing the instruction dependency information and the renamed register to rename the source.
摘要翻译：一种用于重命名用于处理器的源的方法，所述方法包括提供指令，基于所述指令构建指令依赖性信息，基于所述指令依赖性信息来缓存所述指令以提供缓存指令，基于所述高速缓存指令重命名寄存器提供重新命名的寄存器的指令，以及多路复用指令依赖性信息和重命名的寄存器来重命名源。

100. 发明授权

US06804632B2 Distribution of processing activity across processing hardware based on power consumption considerations 有权
标题翻译：基于功耗注意事项分布处理硬件的处理活动
公开(公告)号：US06804632B2
公开(公告)日：2004-10-12
申请号：US10020568
申请日：2001-12-06
申请人： Doron Orenstien , Ronny Ronen
发明人： Doron Orenstien , Ronny Ronen
IPC分类号： G06F906
CPC分类号： G06F9/4856 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24 , Y02D10/32 , Y02D50/20
摘要： Distribution of processing activity across processing hardware based on power consumption and/or thermal considerations. One embodiment includes a plurality of processing units and a monitor to obtain monitor (e.g., power consumption, or temperature or some combination thereof) values from the processing units. The monitor transfers a process from one processing unit to another in response to the monitor values from the processing units.
摘要翻译：基于功耗和/或热考虑分布处理硬件的处理活动。一个实施例包括多个处理单元和监视器以从处理单元获得监视器（例如，功率消耗，或其温度或其组合）值。响应于来自处理单元的监视值，监视器将处理从一个处理单元传送到另一处理单元。

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