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91. 发明授权

US07247905B2 Offset vertical device 失效
标题翻译：偏移垂直装置
公开(公告)号：US07247905B2
公开(公告)日：2007-07-24
申请号：US10813352
申请日：2004-03-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.
摘要翻译：本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

92. 发明申请

US20070047293A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 有权
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20070047293A1
公开(公告)日：2007-03-01
申请号：US11161962
申请日：2005-08-24
申请人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
发明人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

93. 发明授权

US08937345B2 Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact 有权
标题翻译：集成电路包括通过上覆触点与沟槽电容器电连接的有源晶体管
公开(公告)号：US08937345B2
公开(公告)日：2015-01-20
申请号：US13454635
申请日：2012-04-24
申请人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
IPC分类号： H01L27/108 , H01L21/768 , H01L23/485
CPC分类号： H01L21/76895 , H01L23/485 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
摘要翻译：集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器有源晶体管。

94. 发明授权

US07785959B2 Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
标题翻译：在单元中并联连接沟槽电容器的多端口存储器制造方法
公开(公告)号：US07785959B2
公开(公告)日：2010-08-31
申请号：US12316748
申请日：2008-12-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译：提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

95. 发明授权

US07668003B2 Dynamic random access memory circuit, design structure and method 有权
标题翻译：动态随机存取电路，设计结构与方法
公开(公告)号：US07668003B2
公开(公告)日：2010-02-23
申请号：US12108548
申请日：2008-04-24
申请人： John E. Barth, Jr. , Kangguo Cheng , Hoki Kim , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Hoki Kim , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/10829 , G11C7/02 , G11C11/4099 , H01L27/10861 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.
摘要翻译：公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

96. 发明申请

US20090079030A1 Forming SOI Trench Memory with Single-Sided Buried Strap 失效
标题翻译：形成具有单面埋地带的SOI沟槽存储器
公开(公告)号：US20090079030A1
公开(公告)日：2009-03-26
申请号：US12169727
申请日：2008-07-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

97. 发明授权

US07445988B2 Trench memory 有权
标题翻译：沟槽记忆
公开(公告)号：US07445988B2
公开(公告)日：2008-11-04
申请号：US12023175
申请日：2008-01-31
申请人： Kangguo Cheng , Geng Wang
发明人： Kangguo Cheng , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L27/10867
摘要： A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a portion of the doped deposition, deposition of an undoped insulator in the trench and removal of a portion of the doped and undoped insulators.
摘要翻译：提供了一种沟槽器件及其制造方法。沟槽装置具有带有第一部分的套环，该第一部分被掺杂，而第二部分是未掺杂的。部分掺杂的环的制造可以通过在沟槽中沉积掺杂的绝缘体，去除掺杂沉积的一部分，在沟槽中沉积未掺杂的绝缘体以及去除掺杂和未掺杂的绝缘体的一部分来完成。

98. 发明授权

US07408229B2 Structure and method for accurate deep trench resistance measurement 有权
标题翻译：精确深沟槽电阻测量的结构和方法
公开(公告)号：US07408229B2
公开(公告)日：2008-08-05
申请号：US11853045
申请日：2007-09-11
申请人： Kangguo Cheng , Geng Wang
发明人： Kangguo Cheng , Geng Wang
IPC分类号： H01L29/76
CPC分类号： H01L22/34 , H01L27/1087 , H01L29/8605 , H01L2924/0002 , H01L2924/00
摘要： A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a deep trench formed within a semiconductor substrate. The deep trench has a dielectric material formed on upper portions of sidewall surfaces thereof, and includes a conductive fill material therein. A doped buried plate region encompasses a bottom portion of the deep trench, and a doped horizontal n-well band is in electrical contact with an upper portion of the doped buried plate region. A doped vertical n-well band is in electrical contact with the doped horizontal n-well band.
摘要翻译：用于实现在半导体器件中形成的深沟槽的电阻测量的测试结构包括形成在半导体衬底内的深沟槽。深沟槽具有形成在其侧壁表面的上部的介电材料，并且其中包括导电填充材料。掺杂掩埋板区域包围深沟槽的底部，并且掺杂的水平n阱带与掺杂掩埋板区域的上部电接触。掺杂的垂直n阱带与掺杂的水平n阱带电接触。

99. 发明授权

US07384842B1 Methods involving silicon-on-insulator trench memory with implanted plate 有权
标题翻译：涉及具有植入板的绝缘体上硅沟槽存储器的方法
公开(公告)号：US07384842B1
公开(公告)日：2008-06-10
申请号：US12031093
申请日：2008-02-14
申请人： Kangguo Cheng , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions into the substrate and the SOI layer on a first opposing side of the trench and a second opposing side the trench to partially form a capacitor, depositing a node dielectric in the trench, filling the trench with a first polysilicon, removing a portion of the first polysilicon from the trench, removing an exposed portion of the node dielectric, filling the trench with a second polysilicon, masking to define an active region on the hardmask layer, forming shallow trench isolation (STI) such that the STI contacts a portion of the buried oxide layer, removing the hardmask layer, and forming a transistor.
摘要翻译：一种用于制造绝缘体上硅（SOI）沟槽存储器的方法，包括在衬底上形成沟槽，其中掩埋氧化物层设置在衬底上，SOI层设置在掩埋氧化物层上，并且设置硬掩模层在所述SOI层上，将离子注入到所述衬底中并且在所述沟槽的第一相对侧上的所述SOI层和所述沟槽的第二相对侧，以部分地形成电容器，在所述沟槽中沉积节点电介质，用第一多晶硅填充所述沟槽从所述沟槽去除所述第一多晶硅的一部分，去除所述节点电介质的暴露部分，用第二多晶硅填充所述沟槽，以掩蔽以限定所述硬掩模层上的有源区域，形成浅沟槽隔离（STI），使得 STI接触掩埋氧化物层的一部分，去除硬掩模层，并形成晶体管。

100. 发明申请

US20070158724A1 TRENCH MEMORY 有权
标题翻译： TRENCH记忆
公开(公告)号：US20070158724A1
公开(公告)日：2007-07-12
申请号：US11306669
申请日：2006-01-06
申请人： Kangguo Cheng , Geng Wang
发明人： Kangguo Cheng , Geng Wang
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/10867
摘要： A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a portion of the doped deposition, deposition of an undoped insulator in the trench and removal of a portion of the doped and undoped insulators.
摘要翻译：提供了一种沟槽器件及其制造方法。沟槽装置具有带有第一部分的套环，该第一部分被掺杂，而第二部分是未掺杂的。部分掺杂的环的制造可以通过在沟槽中沉积掺杂的绝缘体，去除掺杂沉积的一部分，在沟槽中沉积未掺杂的绝缘体以及去除掺杂和未掺杂的绝缘体的一部分来完成。

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