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91. 发明授权

US06629786B1 Active control of developer time and temperature 失效
标题翻译：主动控制显影时间和温度
公开(公告)号：US06629786B1
公开(公告)日：2003-10-07
申请号：US09845232
申请日：2001-04-30
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G03D500
CPC分类号： G03D5/00
摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译：提供了一种用于调节开发过程的时间和温度的系统。该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。从光栅反射的光被测量系统收集，该系统处理收集的光。通过光栅的光可以类似地由处理所收集的光的测量系统收集。所收集的光表示晶片的各个部分的显影进展。该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。处理器选择性地控制加热装置，以调节晶片各部分的温度。

92. 发明授权

US06448097B1 Measure fluorescence from chemical released during trim etch 失效
标题翻译：测量在修剪蚀刻期间释放的化学物质的荧光
公开(公告)号：US06448097B1
公开(公告)日：2002-09-10
申请号：US09911236
申请日：2001-07-23
申请人： Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： H01L3126
CPC分类号： G01N21/64 , G01N2021/6417 , H01L22/26
摘要： A system and method is provided for determining and controlling development of a semiconductor substrate employing fluorescence spectroscopy. One aspect of the invention relates to a system and method employing fluorescence spectroscopy to facilitate control of a chemical trim etch process during development of a photoresist material layer. The chemical trim etch process comprises applying a trim compound or material to a patterned photoresist. The trim compound or material is diffusable into the sides and top of the patterned resist. The diffused regions of the resist are soluble in a developer, which facilitates creating smaller features in the patterned photoresist. The fluorescence spectroscopy system can be employed to measure isolated and dense gratings or CDs and use the evolution of the CD to determine when to terminate the chemical trim process.
摘要翻译：提供了一种使用荧光光谱法确定和控制半导体衬底的开发的系统和方法。本发明的一个方面涉及使用荧光光谱学来促进在光致抗蚀剂材料层的显影期间控制化学修剪蚀刻工艺的系统和方法。化学修剪蚀刻工艺包括将修剪化合物或材料施加到图案化的光致抗蚀剂上。修整组合物或材料可扩散到图案化抗蚀剂的侧面和顶部。抗蚀剂的扩散区域可溶于显影剂，这有助于在图案化的光致抗蚀剂中产生更小的特征。荧光光谱系统可用于测量孤立和致密的光栅或CD，并使用CD的演变来确定何时终止化学修饰过程。

93. 发明授权

US06335152B1 Use of RTA furnace for photoresist baking 有权
标题翻译：使用RTA炉进行光刻胶烘烤
公开(公告)号：US06335152B1
公开(公告)日：2002-01-01
申请号：US09564408
申请日：2000-05-01
申请人： Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh
发明人： Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh
IPC分类号： G03F738
CPC分类号： G03F7/38
摘要： In one embodiment, the present invention relates to a method of processing an irradiated photoresist involving the steps of placing a substrate having the irradiated photoresist thereon at a first temperature in a rapid thermal anneal furnace; heating the substrate having the irradiated photoresist thereon to a second temperature within about 0.1 seconds to about 10 seconds; cooling the substrate having the irradiated photoresist thereon to a third temperature in a rapid thermal annealing furnace within about 0.1 seconds to about 10 seconds; and developing the irradiated photoresist, wherein the second temperature is higher than the first temperature and the third temperature. In another embodiment, the present invention relates to a system of processing a photoresist, containing a source of actinic radiation and a mask for selectively irradiating a photoresist; a rapid thermal annealing furnace for rapidly heating and rapidly cooling a selectively irradiated photoresist, wherein the rapid heating and rapid cooling are independently conducted within about 0.1 seconds to about 10 seconds; and a developer for developing a rapid thermal annealing furnace heated and selectively irradiated photoresist into a patterned photoresist.
摘要翻译：在一个实施方案中，本发明涉及一种处理被照射的光致抗蚀剂的方法，包括以下步骤：在快速热退火炉中将具有照射光致抗蚀剂的基底在第一温度下放置; 将其上具有照射的光致抗蚀剂的基板加热至约0.1秒至约10秒的第二温度; 将快速热退火炉中具有照射光致抗蚀剂的基板冷却至约0.1秒至约10秒的第三温度; 并且显影所述被照射的光致抗蚀剂，其中所述第二温度高于所述第一温度和所述第三温度。在另一个实施方案中，本发明涉及一种处理含有光化辐射源的光致抗蚀剂的系统和用于选择性地照射光致抗蚀剂的掩模; 快速热退火炉，用于快速加热和快速冷却选择性照射的光致抗蚀剂，其中快速加热和快速冷却在约0.1秒至约10秒内独立进行; 以及用于将快速热退火炉加热并选择性地照射光致抗蚀剂的显影剂加工成图案化的光致抗蚀剂。

94. 发明授权

US6060380A Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication 有权
标题翻译：在集成电路制造中的蚀刻工艺期间使用的抗反射硅氧氮化物硬掩模层
公开(公告)号：US6060380A
公开(公告)日：2000-05-09
申请号：US187391
申请日：1998-11-06
申请人： Ramkumar Subramanian , Bhanwar Singh , Simon Chan , Fei Wang
发明人： Ramkumar Subramanian , Bhanwar Singh , Simon Chan , Fei Wang
IPC分类号： H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76813
摘要： A method for etching openings in an integrated circuit uses siliconoxynitride as a hardmask layer. Because of the relatively low reflectivity of siliconoxynitride, when a photoresist layer is deposited on the siliconoxynitride hardmask layer and is exposed to light, the photoresist layer is patterned more conformingly to a desired pattern. The present invention may be used to particular advantage for etching contiguous trench lines and via holes in a dual damascene etch process for small dimension integrated circuits.
摘要翻译：用于蚀刻集成电路中的开口的方法使用硅氧氮化物作为硬掩模层。由于硅氧氮化物的相对低的反射率，当光致抗蚀剂层沉积在硅氧氮化物硬掩模层上并暴露于光时，光致抗蚀剂层被图案更符合期望的图案。本发明可以用于在用于小尺寸集成电路的双镶嵌蚀刻工艺中蚀刻连续沟槽线和通孔的特别优点。

95. 发明授权

US07310155B1 Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures 失效
标题翻译：使用在线编程的LER和可靠性结构提取工具独立的线边粗糙度（LER）测量
公开(公告)号：US07310155B1
公开(公告)日：2007-12-18
申请号：US10958149
申请日：2004-10-04
申请人： Luigi Capodieci , Amit P. Marathe , Bhanwar Singh , Ramkumar Subramanian
发明人： Luigi Capodieci , Amit P. Marathe , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B11/04 , G01B11/14
CPC分类号： G01B11/303 , G01N21/47 , G01N21/9501
摘要： A system that facilitates extraction of line edge roughness measurements that are independent of proprietorship of a metrology device comprises a structure patterned onto silicon with known line edge roughness values associated therewith. A metrology device obtains line edge roughness measurements from the structure, and a correcting component generates an inverse function based upon a comparison between the known line edge roughness values and the measured line edge roughness values. The metrology device can thereafter measure line edge roughness upon a second structure patterned on the silicon, and the inverse function can be applied to such measured line edge roughness values to enable obtainment of line edge roughness measurements that are independent of proprietorship of the metrology device.
摘要翻译：有助于提取独立于计量装置所有权的线边缘粗糙度测量的系统包括利用与其相关联的已知线边缘粗糙度值图案化到硅上的结构。测量装置从该结构获得线边缘粗糙度测量，并且校正部件基于已知的线边缘粗糙度值与所测量的线边缘粗糙度值之间的比较产生反向函数。测量装置此后可以在硅上图案化的第二结构上测量线边缘粗糙度，并且可以将反函数应用于这种测量的线边缘粗糙度值，以使得能够获得独立于计量装置所有权的线边缘粗糙度测量。

96. 发明授权

US07305645B1 Method for manufacturing place & route based on 2-D forbidden patterns 有权
标题翻译：基于2-D禁止模式制造场所和路线的方法
公开(公告)号：US07305645B1
公开(公告)日：2007-12-04
申请号：US10935488
申请日：2004-09-07
申请人： Luigi Capodieci , Bhanwar Singh , Ramkumar Subramanian
发明人： Luigi Capodieci , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： The present invention is directed towards a system and/or methodology that facilitates controlling routing of blocks on a floor plan in an integrated circuit. A pattern collector receives a partially created routing pattern, and a comparing component makes a comparison between the at least partially created routing pattern with one or more patterns in a library of patterns. Routing is controlled based at least in part upon the comparison.
摘要翻译：本发明涉及一种便于控制集成电路中的平面图上的块的路由的系统和/或方法。模式收集器接收部分创建的路由模式，并且比较组件在至少部分创建的路由模式与模式库中的一个或多个模式之间进行比较。至少部分地基于比较来控制路由。

97. 发明授权

US07251033B1 In-situ reticle contamination detection system at exposure wavelength 有权
标题翻译：曝光波长处原位标线污染检测系统
公开(公告)号：US07251033B1
公开(公告)日：2007-07-31
申请号：US10858757
申请日：2004-06-02
申请人： Khoi Phan , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Khoi Phan , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： G01N21/00
CPC分类号： G01N21/94 , G01N2021/95676 , G03F1/84 , G03F7/70916
摘要： A system and method are provided for detecting contaminants or defects on a reticle in-situ. The system and method provide a system that measures the optical transmission through clear areas on a reticle and determines whether the optical transmission of a reticle has been degraded by contaminants or other defects.
摘要翻译：提供了一种系统和方法来现场检测标线上的污染物或缺陷。该系统和方法提供一种系统，其通过掩模版上的清晰区域测量光学透射，并确定掩模版的光学传输是否已被污染物或其他缺陷降解。

98. 发明授权

US07084988B1 System and method for creation of semiconductor multi-sloped features 失效
标题翻译：用于创建半导体多倾斜特征的系统和方法
公开(公告)号：US07084988B1
公开(公告)日：2006-08-01
申请号：US09893803
申请日：2001-06-28
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B11/24
CPC分类号： H01L22/26
摘要： A system and method for monitoring the creation of semiconductor features with multi-slope profiles by employing scatterometry is provided. The system includes a wafer partitioned into one or more portions and one or more light sources, each light source directing light to one or more devices etched on a wafer, the devices having multi-sloped profiles. Reflected light is collected and converted into data by a measuring system. The data is indicative of the etching at the one or more portions of the wafer. The measuring system provides the data to a process analyzer that determines whether adjustments to etching components are necessary by comparing the data to stored etch parameter values. The system also includes etching components. At least one etch component corresponds to a portion of the wafer and performs the etching thereof. The process analyzer selectively controls the etch components to promote consistent etching of multi-slope profiles/features to compensate for wafer to wafer variations.
摘要翻译：提供了一种通过采用散射法来监测具有多斜率分布的半导体特征的创建的系统和方法。该系统包括分为一个或多个部分和一个或多个光源的晶片，每个光源将光引导到在晶片上蚀刻的一个或多个器件，该器件具有多倾斜轮廓。反射光被测量系统收集并转换成数据。数据表示在晶片的一个或多个部分处的蚀刻。测量系统将数据提供给过程分析仪，通过将数据与存储的蚀刻参数值进行比较来确定是否需要对蚀刻部件进行调整。该系统还包括蚀刻部件。至少一个蚀刻部件对应于晶片的一部分并执行其蚀刻。过程分析器选择性地控制蚀刻部件以促进多斜率分布/特征的一致蚀刻以补偿晶片到晶片的变化。

99. 发明授权

US06879406B1 Use of scatterometry as a control tool in the manufacture of extreme UV masks 失效
标题翻译：使用散射测量作为制造极端紫外线掩模的控制工具
公开(公告)号：US06879406B1
公开(公告)日：2005-04-12
申请号：US10677041
申请日：2003-10-01
申请人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
发明人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： G01B11/24 , G03F1/00 , G03F1/14
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/84
摘要： One aspect of the present invention relates to a system and method for controlling an EUV mask fabrication process using a scatterometer. The system includes an EUV mask fabrication system comprising a translucent substrate having one or more layers of reflective material formed thereon and a patterned photoresist layer as the uppermost layer, a mask inspection system operatively connected to the mask fabrication system for examining the layers as they are being etched and developed by the mask fabrication system and generating data related thereto, and an EUV mask fabrication control system coupled to the mask inspection system for receiving data from the inspection system in order to regulate the mask fabrication system to facilitate obtaining desired critical dimensions. The method involves monitoring the etching of the features, generating data related to the features, and relaying the data to a control system to optimize the EUV mask fabrication process.
摘要翻译：本发明的一个方面涉及使用散射仪控制EUV掩模制造工艺的系统和方法。该系统包括EUV掩模制造系统，该系统包括其上形成有一层或多层反射材料的半透明基材和作为最上层的图案化光致抗蚀剂层，与该掩模制造系统可操作地连接的掩模检查系统，以便像它们一样检查这些层由掩模制造系统蚀刻和显影并产生与之相关的数据，以及耦合到掩模检查系统的EUV掩模制造控制系统，用于从检查系统接收数据，以便调节掩模制造系统以便于获得期望的临界尺寸。该方法包括监测特征的蚀刻，产生与特征有关的数据，以及将数据中继到控制系统以优化EUV掩模制造工艺。

100. 发明授权

US06869888B1 E-beam flood exposure of spin-on material to eliminate voids in vias 失效
标题翻译：旋转材料的电子束暴露以消除通孔中的空隙
公开(公告)号：US06869888B1
公开(公告)日：2005-03-22
申请号：US09901704
申请日：2001-07-11
申请人： Marina V. Plat , Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh
发明人： Marina V. Plat , Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh
IPC分类号： H01L21/027 , H01L21/3105 , H01L21/312 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02134 , H01L21/0276 , H01L21/31058 , H01L21/312 , H01L21/76825
摘要： A method for forming a semiconductor device is described. The method comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. The BARC layer is exposed to an electron beam (e-beam) so that the BARC layer reaches a flow temperature in the at least one hole. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the BARC layer in the at least one hole acts as an etch resistant layer during the etch.
摘要翻译：对半导体装置的形成方法进行说明。该方法包括在半导体衬底上形成第一层。通过第一层形成至少一个孔。在至少一个孔中形成底部抗反射涂层（BARC）层。 BARC层暴露于电子束（电子束），使得BARC层在至少一个孔中达到流动温度。执行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的BARC层在蚀刻期间用作耐蚀刻层。

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