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91. 发明授权

US07596862B2 Method of making a circuitized substrate 失效
标题翻译：制造电路化基板的方法
公开(公告)号：US07596862B2
公开(公告)日：2009-10-06
申请号：US11863820
申请日：2007-09-28
申请人： Frank D. Egitto , Kevin T. Knadle , Andrew M. Seman
发明人： Frank D. Egitto , Kevin T. Knadle , Andrew M. Seman
IPC分类号： H05K3/02
CPC分类号： H05K3/06 , B32B15/08 , B32B15/20 , B32B27/04 , B32B27/06 , B32B27/30 , B32B27/38 , H01L21/32134 , H01L21/4846 , H01L21/76838 , H01L2924/0002 , H05K3/027 , H05K3/061 , H05K3/064 , H05K2203/0369 , H05K2203/1476 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322 , Y10T428/24802 , H01L2924/00
摘要： A method of making the circuitized substrate. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.
摘要翻译：制造电路化基板的方法。电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。导电层包括其中的至少一个侧壁，在导电层中限定开口。所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。

92. 发明授权

US07325299B2 Method of making a circuitized substrate 失效
标题翻译：制造电路化基板的方法
公开(公告)号：US07325299B2
公开(公告)日：2008-02-05
申请号：US11619789
申请日：2007-01-04
申请人： Frank D. Egitto , Kevin T. Knadle , Andrew M. Seman
发明人： Frank D. Egitto , Kevin T. Knadle , Andrew M. Seman
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： H05K3/06 , B32B15/08 , B32B15/20 , B32B27/04 , B32B27/06 , B32B27/30 , B32B27/38 , H01L21/32134 , H01L21/4846 , H01L21/76838 , H01L2924/0002 , H05K3/027 , H05K3/061 , H05K3/064 , H05K2203/0369 , H05K2203/1476 , Y10T29/49117 , Y10T29/49124 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24322 , Y10T428/24802 , H01L2924/00
摘要： A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall in the conductive layer. A layer of patternable material is formed on the substantially planar upper surface and on the interim side wall. A portion of the layer of patternable material on the conductive layer is removed to expose the interim side wall. A portion of the substantially planar upper surface is removed to form a side wall in the layer of patternable material. Portions of the interim side wall in the conductive layer are removed to form a second side wall and a bottom wall defined by the upper surface of the substrate. The second side wall is substantially perpendicular to the bottom wall.
摘要翻译：制造电路化基板的方法。具有基本平坦的上表面的导电层形成在基板的上表面上并与基板的上表面直接机械接触。去除导电层的一部分以在导电层中形成临时侧壁。在基本平坦的上表面和临时侧壁上形成可图案化材料层。去除导电层上图案化材料层的一部分以露出临时侧壁。去除基本平坦的上表面的一部分以在可图案材料层中形成侧壁。去除导电层中的临时侧壁的部分以形成由衬底的上表面限定的第二侧壁和底壁。第二侧壁基本上垂直于底壁。

93. 发明授权

US07309529B2 Structure and method for improved adhesion between two polymer films 失效
标题翻译：用于改善两个聚合物膜之间粘附的结构和方法
公开(公告)号：US07309529B2
公开(公告)日：2007-12-18
申请号：US10985455
申请日：2004-11-10
申请人： Frank D. Egitto , Luis J. Matienzo
发明人： Frank D. Egitto , Luis J. Matienzo
IPC分类号： B32B27/32 , B32B27/38 , B32B27/40 , B32B9/04
CPC分类号： H01L21/02164 , C08J5/12 , C08J2379/08 , H01L21/02118 , H01L21/022 , H01L21/02205 , H01L21/02211 , H01L21/02216 , H01L21/02304 , H01L21/312 , H01L21/31612 , H01L21/76801 , H01L21/76825 , H01L21/76826 , Y10T428/31504 , Y10T428/31507 , Y10T428/31511 , Y10T428/31551 , Y10T428/31598 , Y10T428/31667 , Y10T428/31721 , Y10T428/31855
摘要： A method for improving the adhesion between polyimide layers and the structure formed by the method. A silicon oxide-containing layer is formed on the surface of a polyimide layer and a second layer of polyimide is formed on the silicon oxide-containing layer.
摘要翻译：一种改善聚酰亚胺层之间的粘合性的方法和通过该方法形成的结构。在聚酰亚胺层的表面上形成含氧化硅的层，在含氧化硅的层上形成第二层聚酰亚胺。

94. 发明授权

US07011531B2 Membrane probe with anchored elements 失效
标题翻译：带有锚定元件的膜探针
公开(公告)号：US07011531B2
公开(公告)日：2006-03-14
申请号：US11031859
申请日：2005-01-07
申请人： Frank D. Egitto , Keith J. Miller , Manh-Quan T. Nguyen
发明人： Frank D. Egitto , Keith J. Miller , Manh-Quan T. Nguyen
IPC分类号： H01R12/00
CPC分类号： G01R1/06733 , G01R1/0735 , H01R12/52 , H01R12/7082 , H01R12/714 , H01R2201/20 , H05K3/205 , H05K3/4007 , H05K3/423 , H05K2201/0367 , H05K2201/09745 , H05K2201/09845 , H05K2201/10378 , H05K2203/0369 , H05K2203/0733 , Y10T29/4922
摘要： A structure and method to establish an electrical connection between a tester and an electrical component. A flexible dielectric layer has a first side and a second side. A through via extends through the first side and the second side of the dielectric layer. A blind via is placed in a position that is offset from the through via and extends laterally in a first direction from a section of the first through via to a section of the flexible dielectric layer. The blind via extends in a second direction from the first side of the flexible dielectric layer to a section of the flexible dielectric layer that is between the first side and the second side of the dielectric layer. An electrically conductive member extends through the through via and extends into the blind via, thereby filling the through via and the blind via. The electrically conductive member has a first surface and a second surface. Any distance between the first surface and the second surface is greater than a distance between the first side of the dielectric layer and the second side of the dielectric layer.
摘要翻译：一种在测试仪和电气部件之间建立电气连接的结构和方法。柔性介电层具有第一面和第二面。通孔延伸穿过电介质层的第一侧和第二侧。盲通孔放置在从通孔偏移的位置，并且在从第一通孔的一部分到柔性介电层的一部分的第一方向上横向延伸。盲孔从柔性介电层的第一侧沿第二方向延伸到介电层的第一侧和第二侧之间的柔性介电层的一部分。导电构件延伸穿过通孔并延伸到盲孔中，从而填充通孔和盲孔。导电构件具有第一表面和第二表面。第一表面和第二表面之间的任何距离都大于电介质层的第一面和电介质层的第二面之间的距离。

95. 发明授权

US06656313B2 Structure and method for improved adhesion between two polymer films 有权
公开(公告)号：US06656313B2
公开(公告)日：2003-12-02
申请号：US09878474
申请日：2001-06-11
申请人： Frank D. Egitto , Luis J. Matienzo
发明人： Frank D. Egitto , Luis J. Matienzo
IPC分类号： B32B3100
CPC分类号： H01L21/02164 , C08J5/12 , C08J2379/08 , H01L21/02118 , H01L21/022 , H01L21/02205 , H01L21/02211 , H01L21/02216 , H01L21/02304 , H01L21/312 , H01L21/31612 , H01L21/76801 , H01L21/76825 , H01L21/76826 , Y10T428/31504 , Y10T428/31507 , Y10T428/31511 , Y10T428/31551 , Y10T428/31598 , Y10T428/31667 , Y10T428/31721 , Y10T428/31855
摘要： A method for improving the adhesion between polyimide layers and the structure formed by the method. A silicon oxide-containing layer is formed on the surface of a polyimide layer and a second layer of polyimide is formed on the silicon oxide-containing layer.

96. 发明授权

US06306683B1 Method of forming a flip chip assembly, and a flip chip assembly formed by the method 失效
标题翻译：形成倒装芯片组件的方法，以及通过该方法形成的倒装芯片组件
公开(公告)号：US06306683B1
公开(公告)日：2001-10-23
申请号：US09526569
申请日：2000-03-16
申请人： Jean Dery , Frank D. Egitto , Luis J. Matienzo , Charles Ouellet , Luc Ouellet , David L. Questad , William J. Rudik , Son K. Tran
发明人： Jean Dery , Frank D. Egitto , Luis J. Matienzo , Charles Ouellet , Luc Ouellet , David L. Questad , William J. Rudik , Son K. Tran
IPC分类号： H01L2144
CPC分类号： H01L24/28 , H01L21/563 , H01L24/45 , H01L2224/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/83102 , H01L2224/92125 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , Y10S438/959 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/48
摘要： A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treat with the plasma before they are joined to one another. The plasma treatment improves adhesion between the encapsulant and the IC chip, and between the encapsulant and the chip carrier.
摘要翻译：一种用于形成板上倒装芯片组件的方法。具有聚酰亚胺钝化层的集成电路（IC）芯片通过将IC芯片上的多个接触焊盘电连接到芯片载体上的相应触点的多个焊料凸块而接合到芯片载体。在钝化层的表面和芯片载体的表面之间形成空间。施加等离子体以化学改性芯片载体的表面和IC芯片的钝化层，基本上不使钝化层的表面变粗糙。等离子体是O2等离子体或微波产生的Ar和N2O等离子体。应用底部填充密封材料填充空间。等离子体处理可以在接合步骤之后进行。然后，同时用等离子体处理芯片和芯片载体。或者，IC芯片和芯片载体可以在彼此接合之前用等离子体处理。等离子体处理改善了密封剂和IC芯片之间以及密封剂和芯片载体之间的粘合性。

97. 发明授权

US06284329B1 Method of forming adherent metal components on a polyimide substrate 失效
公开(公告)号：US06284329B1
公开(公告)日：2001-09-04
申请号：US09376901
申请日：1999-08-18
申请人： Luis J. Matienzo , Kim J. Blackwell , Frank D. Egitto , Allan R. Knoll
发明人： Luis J. Matienzo , Kim J. Blackwell , Frank D. Egitto , Allan R. Knoll
IPC分类号： C23C1402
CPC分类号： B32B15/08 , B32B7/12 , B32B38/0008 , B32B2311/12 , B32B2379/08 , C23C14/022 , C23C14/205 , H05K1/0346 , H05K3/381 , H05K2201/0154 , H05K2203/065 , Y10T428/31681 , Y10T428/31721
摘要： A method for attaching adherent metal components, particularly a copper film, on at least one surface of a polyimide substrate is provided. The method comprises the steps of: exposing at least one surface of the polyimide substrate to a reactive gas plasma that provides a level of ion bombardment of the polyimide surface sufficient to disrupt at least a portion of the imide groups on the surface and to form reactive carboxylate groups, carbonyl groups and other carbon-oxygen functional groups on the surface; and then depositing a metal film onto the chemically-modified surface without intervening exposure to air. The present invention also provides a copper-coated polyimide product comprising a polyimide substrate having a substantially smooth and chemically-modified surface and a copper film directly attached to the surface, i.e., the product is free of a polymeric adhesive layer or tie coat between the surface of the polyimide substrate and the copper film.

98. 发明授权

US06250540B1 Fluxless joining process for enriched solders 失效
标题翻译：富集焊剂的无焊接加工工艺
公开(公告)号：US06250540B1
公开(公告)日：2001-06-26
申请号：US09302740
申请日：1999-04-30
申请人： Frank D. Egitto , Luis J. Matienzo
发明人： Frank D. Egitto , Luis J. Matienzo
IPC分类号： B23K100
CPC分类号： B23K35/0244 , B23K1/206 , B23K2101/40 , H05K3/3489
摘要： A process for promoting fluxless soldering of a mass of bulk solder having a bulk ratio of a first metal to a second metal, such as lead-enriched solder that has significantly more lead than tin. The process comprises exposing the bulk solder to energized ions of a sputtering gas in the presence of a halogen, such as fluorine, and forming a surface layer having a desired surface layer ratio of the first to the second metal that is less than the bulk ratio, the surface layer further comprising an uppermost surface film containing the fluorine or other halogen. After the solder exposure and surface-layer formation, the process may further comprise electrically joining the solder to a surface without using externally-applied flux. This process enables the joining step to be performed at less than 300° C., at approximately 180° C.
摘要翻译：一种用于促进具有第一金属与第二金属的体积比的大块焊料的无助焊剂的方法，例如比锡显着更多的铅的富铅焊料。该方法包括在诸如氟的卤素存在下将大块焊料暴露于溅射气体的激发离子，并形成表面层，该表面层具有小于体积比的第一至第二金属的所需表面层比表面层还包含含氟或其它卤素的最上表面膜。在焊料曝光和表面层形成之后，该方法还可以包括将焊料电连接到表面而不使用外部施加的焊剂。该方法使接合步骤能够在低于300℃，约180℃下进行。

99. 发明授权

US6074895A Method of forming a flip chip assembly 失效
标题翻译：形成倒装芯片组件的方法
公开(公告)号：US6074895A
公开(公告)日：2000-06-13
申请号：US936032
申请日：1997-09-23
申请人： Jean Dery , Frank D. Egitto , Luis J. Matienzo , Charles Ouellet , Luc Ouellet , David L. Questad , William J. Rudik , Son K. Tran
发明人： Jean Dery , Frank D. Egitto , Luis J. Matienzo , Charles Ouellet , Luc Ouellet , David L. Questad , William J. Rudik , Son K. Tran
IPC分类号： H01L21/56 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/28 , H01L21/563 , H01L2224/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/83102 , H01L2224/92125 , H01L24/45 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01033 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , Y10S438/959
摘要： A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the a surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O.sub.2 plasma or a microwave-generated Ar and N.sub.2 O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another. The plasma treatment improves adhesion between the encapsulant and the IC chip, and between the encapsulant and the chip carrier.
摘要翻译：一种用于形成板上倒装芯片组件的方法。具有聚酰亚胺钝化层的集成电路（IC）芯片通过将IC芯片上的多个接触焊盘电连接到芯片载体上的相应触点的多个焊料凸块而接合到芯片载体。在钝化层的表面和芯片载体的表面之间形成空间。施加等离子体，以化学改性芯片载体的表面和IC芯片的钝化层，基本上不使钝化层的表面变粗糙。等离子体是O2等离子体或微波产生的Ar和N2O等离子体。应用底部填充密封材料填充空间。等离子体处理可以在接合步骤之后进行。然后，同时用等离子体处理芯片和芯片载体。或者，IC芯片和芯片载体可以在彼此接合之前用等离子体处理。等离子体处理改善了密封剂和IC芯片之间以及密封剂和芯片载体之间的粘合性。

100. 发明授权

US6056831A Process for chemically and mechanically enhancing solder surface properties 失效
标题翻译：化学和机械增强焊料表面性能的工艺
公开(公告)号：US6056831A
公开(公告)日：2000-05-02
申请号：US113445
申请日：1998-07-10
申请人： Frank D. Egitto , Edmond O. Fey , Luis J. Matienzo , David L. Questad , Rajinder S. Rai , Daniel C. Van Hart
发明人： Frank D. Egitto , Edmond O. Fey , Luis J. Matienzo , David L. Questad , Rajinder S. Rai , Daniel C. Van Hart
IPC分类号： B23K35/14 , B23K35/26 , C23C8/00 , C23C26/00 , H05K3/34
CPC分类号： C23C26/00 , B23K35/262 , B23K35/268 , C23C8/00 , H05K3/3457 , H05K2203/092 , H05K2203/095 , Y10S148/901 , Y10S148/903 , Y10T428/12687 , Y10T428/12701 , Y10T428/12708 , Y10T428/12861 , Y10T428/12896
摘要： A process for altering surface properties of a mass of metal alloy solder comprising a first metal and a second metal. The process comprises exposing the mass to energized ions to preferentially sputter atoms of the first metal to form a surface layer ratio of first metal to second metal atoms that is less than the bulk ratio. The solder may be located on the surface of a substrate, wherein the process may further comprise masking the substrate to shield all but a selected area from the ion beam. The sputtering gas may comprises a reactive gas such as oxygen and the substrate may be an organic substrate. The process may further comprise simultaneously exposing the organic substrate to energized ions of the reactive gas to roughen the organic substrate surface.
摘要翻译：一种用于改变包括第一金属和第二金属的金属合金焊料块的表面性质的方法。该方法包括将质量暴露于通电离子以优先溅射第一金属的原子，以形成小于体积比的第一金属与第二金属原子的表面层比。焊料可以位于衬底的表面上，其中该工艺可以进一步包括掩蔽衬底以屏蔽离开所述离子束的所有区域。溅射气体可以包括诸如氧的反应性气体，并且衬底可以是有机衬底。该方法可以进一步包括将有机底物同时暴露于活性气体的激发离子以粗糙化有机基底表面。

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