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91. 发明申请

US20060029069A1 Adapated disk drives executing instructions for I/O command processing 有权
标题翻译：适用于执行I / O命令处理指令的磁盘驱动器
公开(公告)号：US20060029069A1
公开(公告)日：2006-02-09
申请号：US11243116
申请日：2005-10-03
申请人： Charles Frank , Thomas Ludwig , Thomas Hanan , William Babbitt
发明人： Charles Frank , Thomas Ludwig , Thomas Hanan , William Babbitt
IPC分类号： H04L12/56 , H04L12/28 , H04L12/54
CPC分类号： H04L12/66 , H04L12/28 , H04L12/2803 , H04L12/2832 , H04L12/2836 , H04L12/46 , H04L12/4616 , H04L12/4625 , H04L12/4633 , H04L29/12009 , H04L29/12783 , H04L29/12801 , H04L41/00 , H04L61/35 , H04L61/6004 , H04L63/0428 , H04L63/12 , H04L63/20 , H04L67/1097 , H04L69/22 , H04L2012/2849 , H04L2212/00
摘要： Communication protocols, systems, and methods that facilitate communication between disaggregated elements, and also to devices adapted to function as such disaggregated elements, particularly across peer-to-peer (masterless) and include one or more unique features such as packet atomicity, blind ACKs, NAT bridging, locking, multicast spanning and mirroring, and authentication.
摘要翻译：便于在分解的元件之间进行通信的通信协议，系统和方法，以及适于作为这样的分解元素起作用的设备，特别是跨对等（无主），并包括一个或多个独特特征，例如分组原子性，盲ACK NAT桥接，锁定，组播跨接和镜像以及认证。

92. 发明申请

US20050136582A1 Method and device for automated layer generation for double-gate FinFET designs 失效
标题翻译：用于双栅极FinFET设计的自动化层生成的方法和装置
公开(公告)号：US20050136582A1
公开(公告)日：2005-06-23
申请号：US11001297
申请日：2004-12-01
申请人： Ingo Aller , Veit Gernhoefer , Joachim Keinert , Thomas Ludwig
发明人： Ingo Aller , Veit Gernhoefer , Joachim Keinert , Thomas Ludwig
IPC分类号： G03F1/08 , G06F17/50 , H01L21/336 , H01L21/82 , H01L21/8234 , H01L27/04 , H01L27/08 , H01L27/088 , H01L29/786 , H01L21/00
CPC分类号： H01L29/785 , G06F17/5068 , H01L21/823821 , H01L29/66795
摘要： In a FinFET integrated circuit design, a combined cell structure contains two single cell structures at a first design hierarchy having fin shapes, the cell structures are placed adjacent to each other. The combined fin shapes of the two single cell structures at the first design hierarchy lead to a violation of a design rule related to fin topology in the overlapping region. A fin generation tool thus decides not to place the fins in the first design hierarchy. The fin generation is delegated another design hierarchy resulting in the generation of a single combined fin for both single cells.
摘要翻译：在FinFET集成电路设计中，组合单元结构包含具有鳍形状的第一设计层次的两个单个单元结构，单元结构彼此相邻放置。在第一设计层次上的两个单细胞结构的组合翅片形状导致违反与重叠区域中的翅片拓扑相关的设计规则。因此，翅片生成工具决定不将翅片放置在第一设计层级中。翅片生成被委派为另一种设计层次结构，从而为单个单元生成单个组合翅片。

93. 发明授权

US06766968B2 Fuel injection valve 失效
标题翻译：燃油喷射阀
公开(公告)号：US06766968B2
公开(公告)日：2004-07-27
申请号：US10204534
申请日：2002-11-21
申请人： Franz Rieger , Thomas Ludwig , Hans Schlembach , Gottlob Haag , Ulrich Brenner , Michael Huebel , Juergen Stein , Udo Sieber
发明人： Franz Rieger , Thomas Ludwig , Hans Schlembach , Gottlob Haag , Ulrich Brenner , Michael Huebel , Juergen Stein , Udo Sieber
IPC分类号： F02M5100
CPC分类号： F02M51/0671 , F02M61/162 , F02M61/18 , F02M61/1806
摘要： A fuel injector for fuel injection systems in internal combustion engines, including an actuator, a valve needle operable by the actuator for operating a valve-closure member, which, together with a valve-seat surface forms a sealing seat and a swirl device including at least one swirl channel, through which fuel flows with a tangential component relative to a longitudinal axis of the fuel injector. The axial position of a plunger element determines a cross-section of at least one bypass channel that bypasses the at least one swirl channel without a tangential component.

94. 发明授权

US06240848B1 Device for firing a pyrotechnic propellent composition 失效
标题翻译：用于燃烧烟火推进剂组合物的装置
公开(公告)号：US06240848B1
公开(公告)日：2001-06-05
申请号：US09068802
申请日：1998-08-10
申请人： Martin Specht , Thomas Ludwig
发明人： Martin Specht , Thomas Ludwig
IPC分类号： B60R2132
CPC分类号： F42C1/04 , B60R22/4652
摘要： A device for firing a pyrotechnic propellent composition having a sensor mass (3) which for firing purposes releases a locking lever (4) which in the rest position bears lockingly against a ring (9) of the firing pin (1).
摘要翻译：用于点燃具有用于点火目的的传感器质量（3）的烟火推进剂组合物的装置释放锁定杆（4），所述锁定杆在静止位置锁定地抵靠着撞针（1）的环（9）。

95. 发明授权

US5928319A Combined binary/decimal adder unit 失效
标题翻译：组合二进制/十进制加法器单元
公开(公告)号：US5928319A
公开(公告)日：1999-07-27
申请号：US969244
申请日：1997-11-13
申请人： Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
发明人： Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
IPC分类号： G06F7/491 , G06F7/50
CPC分类号： G06F7/4912 , G06F7/507
摘要： A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.
摘要翻译：组合的二进制/十进制加法器单元减少了处理二进制编码十进制操作数的操作延迟，并且允许使用组合的二进制/十进制加法单元的处理器单元的增加的周期速率。对于加法器单元的十进制位数的总和的并行生成和分配，对于每个十进制数位置产生预和。预计总和预期小数位置的进位，并且在产生了最高十进制位数的进位信号之后需要进行六次校正。每个十进制位数的进位信号与操作控制信号组合使用，以选择数位位置的正确预置。

96. 发明授权

US5744996A CMOS integrated semiconductor circuit 失效
标题翻译： CMOS集成半导体电路
公开(公告)号：US5744996A
公开(公告)日：1998-04-28
申请号：US387705
申请日：1995-07-17
申请人： Gunther Kotzle , Volker Kreuter , Thomas Ludwig , Helmut Schettler
发明人： Gunther Kotzle , Volker Kreuter , Thomas Ludwig , Helmut Schettler
IPC分类号： G05F3/20 , H01L27/02 , H03K3/01
CPC分类号： H01L27/0222 , G05F3/205
摘要： An integrated semiconductor circuit for reducing power consumption, employing CMOS technology in which a transistor pair can be operated stably at different supply voltages. At each supply voltage the transistors have an associated threshold voltage which can be set via the well and substrate bias voltages. The substrate of the transistor pair is connected to a substrate bias voltage generator circuit and the well is connected to a well bias voltage generator circuit. An input signal representing the level of the supply voltage sets the respective bias voltages corresponding to the level of the supply voltage. Thus, the threshold voltage of each transistor is adapted to the existing supply voltage, thereby ensuring stable operation of the transistor pair. A battery driven data processing system with the integrated semiconductor circuit can attain an approximate 100 fold extension of the operating time of the battery.
摘要翻译： PCT No.PCT / DE93 / 00443 Sec。 371日期：1995年7月17日 102（e）日期1995年7月17日PCT提交1993年5月21日PCT公布。出版物WO94 / 01890 日期1994年1月20日一种用于降低功耗的集成半导体电路，采用其中晶体管对能够在不同电源电压下稳定运行的CMOS技术。在每个电源电压下，晶体管具有可通过阱和衬底偏置电压来设置的相关阈值电压。晶体管对的基板连接到衬底偏置电压发生器电路，阱连接到阱偏置电压发生器电路。表示电源电压电平的输入信号设定与电源电压的电平对应的各个偏置电压。因此，每个晶体管的阈值电压适应于现有的电源电压，从而确保晶体管对的稳定工作。具有集成半导体电路的电池驱动数据处理系统可以实现电池的工作时间的大约100倍的延长。

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