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91. 发明申请

US20130075821A1 Semiconductor Device Comprising Replacement Gate Electrode Structures and Self-Aligned Contact Elements Formed by a Late Contact Fill 有权
标题翻译：包括替代栅极电极结构的半导体器件和由晚接触填料形成的自对准接触元件
公开(公告)号：US20130075821A1
公开(公告)日：2013-03-28
申请号：US13241915
申请日：2011-09-23
申请人： Peter Baars , Richard Carter , Rolf Stephan
发明人： Peter Baars , Richard Carter , Rolf Stephan
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/76814 , H01L29/66545 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.
摘要翻译：当在基于更换栅极方法的高k金属栅电极结构的复杂半导体器件中形成自对准接触元件时，自对准接触开口用适当的填充材料填充，例如多晶硅而栅电极结构基于可相对于牺牲填充材料以高选择性去除的占位符材料提供。以这种方式，高k金属栅电极结构可以在去除牺牲填充材料之前用适当的接触材料实际填充接触开口之前完成。在一个说明性实施例中，栅电极结构的占位符材料以硅/锗材料的形式提供。

92. 发明申请

US20130075820A1 Superior Integrity of High-K Metal Gate Stacks by Forming STI Regions After Gate Metals 有权
标题翻译：高K金属栅极堆叠通过在栅极金属之间形成STI区域具有卓越的完整性
公开(公告)号：US20130075820A1
公开(公告)日：2013-03-28
申请号：US13239943
申请日：2011-09-22
申请人： Thilo Scheiper , Peter Baars
发明人： Thilo Scheiper , Peter Baars
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/336
CPC分类号： H01L21/76232 , H01L21/823807 , H01L21/823842 , H01L21/823878
摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in designing the overall process flow may be accomplished by forming and patterning the sensitive gate materials prior to forming isolation regions.
摘要翻译：当在早期制造阶段形成复杂的高k金属栅极电极结构时，可以通过在形成隔离物之前形成和图案化敏感栅极材料来实现优异的工艺鲁棒性，降低的屈服损失和提高设计整个工艺流程的灵活性地区。

93. 发明申请

US20130049103A1 REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL 有权
公开(公告)号：US20130049103A1
公开(公告)日：2013-02-28
申请号：US13215635
申请日：2011-08-23
申请人： Till Schloesser , Peter Baars , Frank Jakubowski
发明人： Till Schloesser , Peter Baars , Frank Jakubowski
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/42356 , H01L29/4236 , H01L29/42364 , H01L29/42372 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66621 , H01L29/78 , H01L29/7833 , H01L29/7848
摘要： An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.

94. 发明授权

US08377773B1 Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask 有权
标题翻译：晶体管具有基于硬掩模的早期处理阶段形成的沟道半导体合金
公开(公告)号：US08377773B1
公开(公告)日：2013-02-19
申请号：US13285600
申请日：2011-10-31
申请人： Thilo Scheiper , Peter Baars
发明人： Thilo Scheiper , Peter Baars
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878
摘要： Generally, the present disclosure is directed to methods for adjusting transistor characteristics by forming a semiconductor alloy in the channel region of the transistor during early device processing. One disclosed method includes forming an isolation structure in a semiconductor layer of a semiconductor device and in a threshold voltage adjusting semiconductor alloy formed on the semiconductor layer, the isolation structure laterally separating a first active region and a second active region. The method also includes introducing a first and second well dopant species through the threshold voltage adjusting semiconductor alloy and into the first and second active regions, respectively, then removing the threshold voltage adjusting semiconductor alloy selectively from the second active region, and forming a first gate electrode structure of a first transistor on the threshold voltage adjusting semiconductor alloy of the first active region a second gate electrode structure of a second transistor on the second active region.
摘要翻译：通常，本公开涉及通过在早期器件处理期间在晶体管的沟道区域中形成半导体合金来调整晶体管特性的方法。一种公开的方法包括在半导体器件的半导体层中形成隔离结构，以及在半导体层上形成的阈值电压调节半导体合金中，隔离结构横向分离第一有源区和第二有源区。该方法还包括分别通过阈值电压调节半导体合金引入第一和第二阱掺杂剂物质并分别进入第一和第二有源区，然后从第二有源区选择性地去除阈值电压调整半导体合金，以及形成第一栅极在第一有源区的阈值电压调节半导体合金上的第一晶体管的电极结构，第二有源区上的第二晶体管的第二栅电极结构。

95. 发明申请

US20120299160A1 Method of Forming Contacts for Devices with Multiple Stress Liners 有权
标题翻译：形成具有多个应力衬垫的装置的触点的方法
公开(公告)号：US20120299160A1
公开(公告)日：2012-11-29
申请号：US13116672
申请日：2011-05-26
申请人： Peter Baars , Marco Lepper , Thilo Scheiper
发明人： Peter Baars , Marco Lepper , Thilo Scheiper
IPC分类号： H01L21/311 , H01L23/58
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823871
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括执行第一处理操作以在半导体衬底的第一区域上方形成第一蚀刻停止层，其中将形成第一类型的晶体管器件，以及形成至少高于第一类型的第一应力诱导层所述第一区域中的所述蚀刻停止层，其中所述第一应力诱导层适于在所述第一类型晶体管的沟道区域中引起应力。该方法还包括：在形成第一蚀刻停止层之后，执行第二处理操作，形成第二蚀刻停止层，该第二蚀刻停止层位于衬底的第二区域的第二区域上方，在该第二区域将形成第二类型的晶体管器件，并且形成第二应力诱导层至少在第二区域中的第二蚀刻停止层上方，其中第二应力诱导层适于在第二类型晶体管的沟道区域中引起应力。在一个具体示例中，第一和第二蚀刻停止层可以具有相同的近似厚度。

96. 发明申请

US20120248551A1 MOL INSITU PT REWORK SEQUENCE 有权
标题翻译： MOL INSITU PT REWORK序列
公开(公告)号：US20120248551A1
公开(公告)日：2012-10-04
申请号：US13079492
申请日：2011-04-04
申请人： Peter Baars , Marco Lepper , Uwe Kahler , Vivien Schroeder
发明人： Peter Baars , Marco Lepper , Uwe Kahler , Vivien Schroeder
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/2855 , H01L21/02068 , H01L21/28518 , H01L21/32134 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.
摘要翻译：在形成含Pt的NiSi之后剩余的Pt残余物的量通过在形成浇口间隔件的同时进行O2闪光，然后清洗并应用Aqua Regia的第二次应用来减少。实施例包括在半导体衬底上溅射沉积Ni / Pt层，退火Ni / Pt层，湿剥离未反应的Ni，退火Ni剥离的Ni / Pt层，从退火的Ni / Pt层剥离未反应的Pt，例如， Aqua Regia，用氧等离子体处理Pt剥离的Ni / Pt层，清洁Ni / Pt层，以及从清洁的Ni / Pt层剥离未反应的Pt，例如，通过第二次应用Aqua Regia。

97. 发明申请

US20120211844A1 Semiconductor Device Comprising Self-Aligned Contact Elements and a Replacement Gate Electrode Structure 有权
标题翻译：包括自对准接触元件和替代栅电极结构的半导体器件
公开(公告)号：US20120211844A1
公开(公告)日：2012-08-23
申请号：US13371049
申请日：2012-02-10
申请人： Till Schloesser , Peter Baars , Frank Jakubowski
发明人： Till Schloesser , Peter Baars , Frank Jakubowski
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L29/78 , H01L21/28518 , H01L21/28525 , H01L21/288 , H01L21/76816 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.
摘要翻译：当形成包括高k金属栅电极结构的复杂半导体器件时，可以使用升高的漏极和源极配置来控制在执行替代栅极接近时的高度，从而为形成接触元件提供优越的条件，并且还获得良好可控的减小的门高。

98. 发明申请

US20120211837A1 SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS 有权
标题翻译：包含自对准接触元件的半导体器件
公开(公告)号：US20120211837A1
公开(公告)日：2012-08-23
申请号：US13372604
申请日：2012-02-14
申请人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
发明人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
IPC分类号： H01L21/28 , H01L21/283 , H01L27/088
CPC分类号： H01L21/823475 , H01L21/28518 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823437 , H01L29/66636 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.
摘要翻译：当形成复杂的半导体器件时，可以在替换栅极电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准接触方式结合使用。

99. 发明申请

US20120153398A1 Encapsulation of Closely Spaced Gate Electrode Structures 有权
标题翻译：密封栅电极结构的封装
公开(公告)号：US20120153398A1
公开(公告)日：2012-06-21
申请号：US12974037
申请日：2010-12-21
申请人： Peter Baars , Richard Carter , Andy Wei
发明人： Peter Baars , Richard Carter , Andy Wei
IPC分类号： H01L27/092 , H01L21/8234 , H01L29/772 , H01L21/28
CPC分类号： H01L27/092 , H01L21/28512 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L23/28 , H01L23/485 , H01L29/6656 , H01L29/66628 , H01L29/7834 , H01L29/7847 , H01L2924/0002 , H01L2924/00
摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.
摘要翻译：通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与使用通常可获得的光刻技术形成的窄接触元件。一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

100. 发明授权

US08202739B2 Dopant marker for precise recess control 有权
标题翻译：用于精确凹槽控制的掺杂标记
公开(公告)号：US08202739B2
公开(公告)日：2012-06-19
申请号：US12947150
申请日：2010-11-16
申请人： Dmytro Chumakov , Peter Baars
发明人： Dmytro Chumakov , Peter Baars
IPC分类号： H01L21/00 , H01L21/66 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31053 , H01L22/12 , H01L22/26
摘要： A semiconductor device is formed by implanting recess markers in a material during deposition and using the recess markers during etching of the material for precise in-situ removal rate definition and removal homogeneity-over-radius definition. An embodiment includes depositing a layer of material on a substrate, implanting first and second dopants in the material at first and second predetermined times during deposition of the material, etching the material, detecting the depths of the first and second dopants during etching, calculating the removal rate of the material in situ from the depths of the first and second dopants, and determining from the removal rate a stop position for etching. Embodiments further include depositing a layer of material on a substrate, laterally implanting a first dopant and a second dopant in the material at a predetermined depth during deposition of the material, etching the material, detecting the positions and intensities of the first and second dopants during etching, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants. Embodiments further include in situ corrective action for the removal process based on the determined removal rate and lateral homogeneity.
摘要翻译：半导体器件是通过在沉积期间将凹陷标记物注入材料而形成的，并且在蚀刻材料期间使用凹陷标记物，以精确的原位去除速率定义和去除均匀性超半径的定义。一个实施例包括在衬底上沉积材料层，在材料沉积期间的第一和第二预定时间内在材料中注入第一和第二掺杂剂，蚀刻材料，在蚀刻期间检测第一和第二掺杂剂的深度，计算从第一和第二掺杂剂的深度原位去除材料的去除速率，并从去除速率确定用于蚀刻的停止位置。实施例还包括在衬底上沉积材料层，在材料沉积期间以预定深度横向注入材料中的第一掺杂剂和第二掺杂剂，蚀刻材料，检测第一和第二掺杂剂的位置和强度从第一和第二掺杂剂的强度刻蚀和计算原位材料的侧向均匀性。实施例还包括基于确定的去除速率和横向均匀性的去除过程的原位校正作用。

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