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91. 发明授权

US06246627B1 Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof 有权
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置及其方法
公开(公告)号：US06246627B1
公开(公告)日：2001-06-12
申请号：US09397239
申请日：1999-09-16
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C514
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

92. 发明授权

US06226583B1 Control device for continuously variable transmission 有权
标题翻译：无级变速器控制装置
公开(公告)号：US06226583B1
公开(公告)日：2001-05-01
申请号：US09158499
申请日：1998-09-23
申请人： Toru Iwata
发明人： Toru Iwata
IPC分类号： G06F700
CPC分类号： F16H61/6648 , F16H59/54 , F16H2059/506 , Y10T477/624 , Y10T477/65
摘要： A continuously variable transmission of an automobile which varies the drive ratio arbitrarily between an input axis and an output axis is combined with a traction control device for example which performs braking corresponding to vehicle running conditions and irrespective of the accelerator pedal depression. A microprocessor calculates the vehicle speed from the rotation speed of the output axis, calculates the target drive ratio depending on the vehicle speed, and controls the drive ratio of the continuously variable transmission to be equal to the target ratio. When the brake operation device performs braking, fluctuation of the drive ratio based on the rotation variation of the output axis is prevented by the correction of the drive ratio in the upshift direction.
摘要翻译：将输入轴与输出轴之间的驱动比任意变化的汽车的无级变速器与例如对应于车辆行驶状态进行制动的牵引力控制装置进行组合，并且与加速器踏板下压无关。微处理器根据输出轴的转速计算车速，根据车速计算目标驱动比，并将无级变速器的驱动比控制为目标比。当制动操作装置执行制动时，通过校正升档方向上的驱动比来防止基于输出轴的旋转变化的驱动比的波动。

93. 发明授权

US6145065A Memory access buffer and reordering apparatus using priorities 失效
标题翻译：使用优先级的存储器访问缓冲器和重新排序装置
公开(公告)号：US6145065A
公开(公告)日：2000-11-07
申请号：US67899
申请日：1998-04-29
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/1631
摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.
摘要翻译：目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问主存储部分不管数据传输，从而流水线地址输入周期。此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

94. 发明授权

US6118309A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：US6118309A
公开(公告)日：2000-09-12
申请号：US121191
申请日：1998-07-23
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G11C8/10 , H03K19/00 , H03K19/0948 , H03K19/096
CPC分类号： H03K19/0963 , G11C8/10 , H03K19/0016 , H03K19/0948
摘要： A semiconductor circuit includes an input, an output, and a first transistor and a second transistor coupled in series to a power source. The first transistor is coupled closer to the power source than the second transistor is, and the first transistor has a higher threshold voltage than a threshold voltage of the second transistor. The semiconductor circuit further includes a capacitor which is coupled between the first transistor and the second transistor.
摘要翻译：半导体电路包括输入，输出以及串联耦合到电源的第一晶体管和第二晶体管。第一晶体管比第二晶体管更靠近电源耦合，并且第一晶体管具有比第二晶体管的阈值电压更高的阈值电压。半导体电路还包括耦合在第一晶体管和第二晶体管之间的电容器。

95. 发明授权

US5970018A Semiconductor integrated circuit and decode circuit for memory 失效
标题翻译：半导体集成电路和存储器解码电路
公开(公告)号：US5970018A
公开(公告)日：1999-10-19
申请号：US974560
申请日：1997-11-19
申请人： Toru Iwata , Hironori Akamatsu
发明人： Toru Iwata , Hironori Akamatsu
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C8/10
摘要： In plural internal logic circuits, plural transistors having the same function are merged into a single merged transistor. This merged transistor is interposed between a ground and a virtual ground line connected with a ground node of an inverter included in each of the internal logic circuits, and has a threshold voltage higher than a threshold voltage of a transistor included in each inverter. The merged transistor is controlled in accordance with a block selecting signal. Since the merged transistor is merged among the internal logic circuits, its gate width can be set larger, resulting in attaining a high speed operation of each inverter. During a standby, a leakage current can be suppressed since the merged transistor is in an off-state. During an operation, a leakage current can be suppressed in an unselected circuit block since the merged transistor is in an off-state. Accordingly, while suppressing increase of the circuit area, the internal logic circuits can attain a high speed operation and a leakage current can be minimized during both a standby and an operation.
摘要翻译：在多个内部逻辑电路中，具有相同功能的多个晶体管被合并成单个合并晶体管。该合并后的晶体管被插入在与各内部逻辑电路中包含的逆变器的接地节点连接的地与虚拟地线之间，并且具有比每个逆变器所包含的晶体管的阈值电压高的阈值电压。合并晶体管根据块选择信号进行控制。由于合并的晶体管在内部逻辑电路之间合并，所以其栅极宽度可以设定得更大，从而达到每个逆变器的高速运行。在待机期间，由于合并晶体管处于截止状态，所以可以抑制泄漏电流。在操作期间，由于合并晶体管处于截止状态，所以在未选择的电路块中可以抑制漏电流。因此，在抑制电路面积增加的同时，内部逻辑电路能够实现高速运转，并且在备用和运转两者期间可以使漏电流最小化。

96. 发明授权

US5933050A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：US5933050A
公开(公告)日：1999-08-03
申请号：US862017
申请日：1997-05-22
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G11C8/10 , H03K19/00 , H03K19/0948 , H03K19/096
CPC分类号： H03K19/0963 , G11C8/10 , H03K19/0016 , H03K19/0948
摘要： A semiconductor circuit includes an input, an output, and a first transistor and a second transistor coupled in series to a power source. The first transistor is coupled closer to the power source than the second transistor is, and the first transistor has a higher threshold voltage than a threshold voltage of the second transistor. The semiconductor circuit further includes a capacitor which in coupled between the first transistor and the second transistor.
摘要翻译：半导体电路包括输入，输出以及串联耦合到电源的第一晶体管和第二晶体管。第一晶体管比第二晶体管更靠近电源耦合，并且第一晶体管具有比第二晶体管的阈值电压更高的阈值电压。半导体电路还包括耦合在第一晶体管和第二晶体管之间的电容器。

97. 发明授权

US5732380A System for controlling driving torque of vehicle 失效
标题翻译：控制车辆行驶扭矩的系统
公开(公告)号：US5732380A
公开(公告)日：1998-03-24
申请号：US565611
申请日：1995-11-29
申请人： Toru Iwata
发明人： Toru Iwata
IPC分类号： F02D43/00 , B60K28/16 , F02D17/02 , F02D29/02 , F02D41/22 , F02D45/00 , G06G7/76
CPC分类号： B60K28/16
摘要： In order to provide an accurate traction control by closing a second throttle valve provided in series to an accelerator-operated ordinary throttle valve, with a simplified actuator, a control system for reducing a vehicle driving torque employs one or more sensors for sensing a second vehicle operating parameter representing a road surface friction coefficient (.mu.) or a driver's command for acceleration, in addition to sensors for sensing a first vehicle operating parameter representing a drive wheel slip. When the road surface friction coefficient is high or when the driver depresses the accelerator pedal hard, the control system restrains the closing operation of the second throttle valve in accordance with the second parameter even though the closure of the second throttle valve is requested by the first parameter.
摘要翻译：为了通过闭合与加速器操作的普通节流阀串联设置的第二节流阀，通过简化的致动器来提供精确的牵引力控制，用于减小车辆驱动转矩的控制系统使用一个或多个传感器来感测第二车辆除了用于感测表示驱动轮滑移的第一车辆操作参数的传感器之外，还包括表示路面摩擦系数（μ）或驾驶员的加速指令的操作参数。当路面摩擦系数较大或驾驶员踩下加速踏板时，控制系统根据第二参数来限制第二节流阀的关闭动作，即使第二节流阀的关闭是由第一节气门参数。

98. 发明授权

US5654913A Apparatus and method for extending data retention time of semiconductor storage circuit 失效
标题翻译：用于延长半导体存储电路的数据保留时间的装置和方法
公开(公告)号：US5654913A
公开(公告)日：1997-08-05
申请号：US597250
申请日：1996-02-06
申请人： Tetsuyuki Fukushima , Hiroyuki Yamauchi , Toru Iwata
发明人： Tetsuyuki Fukushima , Hiroyuki Yamauchi , Toru Iwata
IPC分类号： G11C11/4074 , G11C11/408 , G11C11/24
CPC分类号： G11C11/4074 , G11C11/4085
摘要： In halt period during standby time, a cell plate node potential switching circuit changes the potential of a cell plate node to a low potential that is lower than a high potential adopted in a burst refresh operation. As a result, a potential difference between both ends of a PN junction of a memory cell transistor is decreased, thereby suppressing a leakage current flowing through the PN junction. Simultaneously, a word driver circuit changes the potential of a word line to a negative potential that is lower than a normal potential adopted in the burst refresh operation. As a result, an off state of the memory cell transistor is enhanced owing to decrease of a gate-source voltage thereof, thereby suppressing a leakage current flowing from the bit line to a charge storage node. Accordingly, a leakage current flowing through the PN junction of the memory cell transistor and a leakage current flowing from the bit line through the memory cell transistor to the charge storage node are both suppressed during the standby time. Thus, a refresh interval is elongated so as to decrease power consumption.
摘要翻译：在待机时间期间，电池板节点电位切换电路将电池板节点的电位改变为低于突发刷新操作中采用的高电位的低电位。结果，存储单元晶体管的PN结的两端之间的电位差减小，从而抑制流过PN结的漏电流。同时，字驱动器电路将字线的电位改变为低于突发刷新操作中采用的正常电位的负电位。结果，由于栅极 - 源极电压的降低，存储单元晶体管的截止状态被增强，从而抑制从位线流向电荷存储节点的漏电流。因此，在待机时间期间，都会抑制流过存储单元晶体管的PN结的漏电流和从存储单元晶体管的位线流向电荷存储节点的漏电流。因此，延长刷新间隔以降低功耗。

99. 发明授权

US5652729A Semiconductor integrated circuit apparatus and method of adjusting refresh timer cycle 失效
标题翻译：半导体集成电路设备及其调整刷新定时器周期的方法
公开(公告)号：US5652729A
公开(公告)日：1997-07-29
申请号：US597256
申请日：1996-02-06
申请人： Toru Iwata , Hiroyuki Yamauchi
发明人： Toru Iwata , Hiroyuki Yamauchi
IPC分类号： G11C11/406 , G11C13/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40626 , G11C2211/4068
摘要： A semiconductor Integrated circuit apparatus that has memory cell array, and a refresh timer which outputs a refresh signal for holding data of the memory cell array. The apparatus also has a leak monitoring circuit for detecting a voltage drop associated with a leak current from the memory cell array of a main memory, and a pulse generating circuit for outputting the refresh signal. The leak monitoring circuit is formed by a dummy memory cell array, which is formed by memory cells having the same structure as the memory cells of the main memory, a potential comparator for comparing a potential which is outputted from the dummy memory cell array with a predetermined potential, and leak accelerating means for accelerating the potential decrease speed of the dummy memory cell array.
摘要翻译：具有存储单元阵列的半导体集成电路装置和输出用于保持存储单元阵列的数据的刷新信号的刷新定时器。该装置还具有用于检测与来自主存储器的存储单元阵列的泄漏电流相关联的电压降的泄漏监测电路和用于输出刷新信号的脉冲发生电路。泄漏监视电路由虚拟存储单元阵列形成，该虚拟存储单元阵列由具有与主存储器的存储单元相同结构的存储单元形成，用于将从虚拟存储单元阵列输出的电位与以及用于加速虚拟存储单元阵列的潜在降低速度的泄漏加速装置。

100. 发明授权

US5566776A Differential limit torque control apparatus 失效
标题翻译：差速限位转矩控制装置
公开(公告)号：US5566776A
公开(公告)日：1996-10-22
申请号：US402220
申请日：1995-03-10
申请人： Toru Iwata
发明人： Toru Iwata
IPC分类号： B60W10/04 , B60K28/16 , B60T8/175 , B60W10/06 , B60W10/10 , B60W10/18 , B60W10/188 , F02D29/02 , F02D41/04
CPC分类号： B60K28/16 , B60W2510/0604
摘要： A traction control apparatus for use with an automotive vehicle having an internal combustion engine through which an output drive is transmitted to drive road wheels. A demand for first traction control is produced based on a slippage produced on the drive road wheels during acceleration. The first traction control demand includes a normal demand for first traction control continuing for a time shorter than a limit time and an exceptional demand for first traction control continuing over the limit time. A limit value is set for the number of times the exceptional demand is permitted. In response to the first traction control demand, at least one of fuelcut control and ignition control is performed to reduce the engine output drive. The first traction control demand is ignored when the number of times the exceptional demand has occurred reaches the limit value.
摘要翻译：一种用于具有内燃机的机动车辆的牵引力控制装置，通过该内燃机传输输出驱动器来驱动车轮。基于在加速期间在驱动车轮上产生的滑移产生对第一牵引力控制的需求。第一牵引力控制需求包括对第一牵引力控制的正常需求持续时间短于限制时间，并且在极限时间内持续第一牵引力控制的异常要求。对允许异常要求的次数设定限制值。响应于第一牵引力控制要求，执行燃料切断控制和点火控制中的至少一个以减少发动机输出驱动。当异常需求发生的次数达到极限值时，第一个牵引力控制需求被忽略。

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