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91. 发明申请

US20130078774A1 METHOD FOR FORMING DOPE REGIONS WITH RAPID THERMAL PROCESS 审中-公开
标题翻译：用快速热处理法形成区域的方法
公开(公告)号：US20130078774A1
公开(公告)日：2013-03-28
申请号：US13240931
申请日：2011-09-22
申请人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jeng-Hsing Jang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/223 , H01L21/268 , H01L21/823814
摘要： The invention provides a method for forming a semiconductor device, including providing a substrate, forming a gate dielectric layer, forming a gate electrode on the gate dielectric layer, forming a spacer on sidewalls of the gate dielectric layer and the gate electrode, and using a rapid thermal process (RTP) apparatus comprising a plurality of lamps and a bias applying system to dope the substrate to form a source/drain region, wherein in the RTP apparatus, gaseous dopant species are illuminated by the lamps to be excited for transference gaseous dopant species to dopant ions and the dopant ions are moved by a bias from the bias applying system to be doped into the substrate.
摘要翻译：本发明提供一种用于形成半导体器件的方法，包括提供衬底，形成栅极电介质层，在栅极电介质层上形成栅电极，在栅极电介质层和栅电极的侧壁上形成间隔物，并使用包括多个灯的快速热处理（RTP）装置和用于掺杂衬底以形成源极/漏极区域的偏置施加系统，其中在RTP装置中，气体掺杂物质被待激发的灯照射以用于转移气体掺杂剂物质与掺杂剂离子和掺杂剂离子通过来自偏置施加系统的偏压移动以掺杂到衬底中。

92. 发明申请

US20130071992A1 SEMICONDUCTOR PROCESS 审中-公开
标题翻译：半导体工艺
公开(公告)号：US20130071992A1
公开(公告)日：2013-03-21
申请号：US13237975
申请日：2011-09-21
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/762
CPC分类号： H01L21/762 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02664
摘要： A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer.
摘要翻译：提供半导体工艺。绝缘层形成在半导体衬底上。去除绝缘层的一部分，以便形成多个隔离结构和布置在隔离结构之间并露出半导体衬底的网孔。通过进行选择性生长处理，从由网眼露出的半导体衬底的表面形成半导体层，使得隔离结构设置在半导体层中。

93. 发明申请

US20130071790A1 METHOD OF FORMING AN ETCH MASK 有权
标题翻译：形成蚀刻掩模的方法
公开(公告)号：US20130071790A1
公开(公告)日：2013-03-21
申请号：US13233039
申请日：2011-09-15
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G03F7/20
CPC分类号： G03F7/094 , G03F7/095 , G03F7/32 , G03F7/38 , H01L21/0275 , H01L21/0277 , H01L21/32139
摘要： A method of forming an etch mask includes: providing a substrate having thereon a material layer to be etched; forming a hard mask layer consisting of a radiation-sensitive, single-layer resist material on the material layer; exposing the hard mask layer to actinic energy to change solvent solubility of exposed regions of the hard mask layer; and subjecting the hard mask layer to water treatment to remove the exposed regions of the hard mask layer, thereby forming a masking pattern consisting of unexposed regions of the hard mask layer.
摘要翻译：形成蚀刻掩模的方法包括：提供其上具有要蚀刻的材料层的基板; 在材料层上形成由辐射敏感的单层抗蚀剂材料组成的硬掩模层; 将硬掩模层暴露于光化能以改变硬掩模层的暴露区域的溶剂溶解度; 并对硬掩模层进行水处理以除去硬掩模层的暴露区域，从而形成由硬掩模层的未曝光区域构成的掩模图案。

94. 发明申请

US20130069235A1 BONDING PAD STRUCTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的接合焊盘结构
公开(公告)号：US20130069235A1
公开(公告)日：2013-03-21
申请号：US13235491
申请日：2011-09-18
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05085 , H01L2224/05095 , H01L2224/05624
摘要： A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; anda plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.
摘要翻译：焊盘结构包括其上具有包括至少最上面的IMD层的多个金属间电介质（IMD）层的半导体衬底; 可焊接金属焊盘层，其设置在焊盘形成区域内的最上层IMD层的表面上; 覆盖可焊接金属焊盘层的周边和最上面的IMD层的表面的钝化层; 以及设置在焊盘形成区域的环形区域内的最上层IMD层中的多个通孔，其中通孔塞不形成在焊盘形成区域的中心区域中。

95. 发明申请

US20130017684A1 PROCESS OF FORMING SLIT IN SUBSTRATE 有权
标题翻译：在基板上形成缝隙的过程
公开(公告)号：US20130017684A1
公开(公告)日：2013-01-17
申请号：US13179581
申请日：2011-07-11
申请人： Wen-Chieh Wang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Wen-Chieh Wang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/306
CPC分类号： H01L21/3065 , H01L21/3085
摘要： A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl2, CF4 and CHF3, a molar ratio of CF4 to CHF3 is about 0.5-0.8, and a molar ratio of F to Cl is about 0.4-0.8, for example. Further, the step of performing the etching process simultaneously removes the mask layer.
摘要翻译：提供了在基板中形成狭缝的工艺。在基板上形成掩模层，其中掩模层不包括碳。通过使用掩模层作为掩模，进行蚀刻处理，以便在衬底中形成狭缝。蚀刻气体包括Cl 2，CF 4和CHF 3，CF 4与CHF 3的摩尔比为约0.5-0.8，F与Cl的摩尔比例如约为0.4-0.8。此外，进行蚀刻处理的步骤同时去除掩模层。

96. 发明申请

US20120309192A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20120309192A1
公开(公告)日：2012-12-06
申请号：US13154427
申请日：2011-06-06
申请人： Wen-Chieh Wang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Wen-Chieh Wang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/768
CPC分类号： H01L29/66621 , H01L21/26506 , H01L21/26513 , H01L27/10876
摘要： A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.
摘要翻译：提供半导体工艺。在衬底上形成掩模层，并具有暴露衬底的一部分的第一开口。使用掩模层作为掩模，在基板上进行干蚀刻处理，以在其中形成第二开口。第二开口具有底部和从底部向上并向外延伸的侧壁，其中底部由第一开口暴露，并且侧壁被掩模层覆盖。使用掩模层作为掩模，在底部进行垂直离子注入工艺。进行转换处理，以在第二开口的侧壁和底部形成转换层，其中侧壁上的转换层的厚度大于底部上的转换层的厚度。

97. 发明申请

US20120305525A1 METHOD OF REDUCING STRIATION ON A SIDEWALL OF A RECESS 审中-公开
标题翻译：减少碰撞的障碍的方法
公开(公告)号：US20120305525A1
公开(公告)日：2012-12-06
申请号：US13149861
申请日：2011-05-31
申请人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
发明人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： C23F1/00 , B05D3/10
CPC分类号： G03F7/40 , G03F7/405 , H01L21/0273 , H01L21/3086
摘要： A method of reducing striation on a sidewall of a recess is provided. The method includes the steps of providing a substrate covered with a photoresist layer. Then, the photoresist layer is etched to form a patterned photoresist layer. Later, a repairing process is performed by treating the patterned photoresist layer with a repairing gas which is selected from the group consisting of CF4, HBr, O2 and He. Next, the substrate is etched by taking the patterned photoresist layer as a mask after the repairing process. Finally, the patterned photoresist layer is removed.
摘要翻译：提供一种减少凹槽侧壁上的条纹的方法。该方法包括提供被光致抗蚀剂层覆盖的基底的步骤。然后，蚀刻光致抗蚀剂层以形成图案化的光致抗蚀剂层。然后，通过用选自CF 4，HBr，O 2和He的修复气体处理图案化的光致抗蚀剂层来进行修复过程。接下来，在修复处理之后，通过将图案化的光致抗蚀剂层作为掩模来蚀刻基板。最后，去除图案化的光致抗蚀剂层。

98. 发明申请

US20120302060A1 METHOD FOR MANUFACTURING MEMORY DEVICE 有权
标题翻译：制造存储器件的方法
公开(公告)号：US20120302060A1
公开(公告)日：2012-11-29
申请号：US13115039
申请日：2011-05-24
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/768
CPC分类号： H01L27/10873 , H01L21/76834 , H01L21/7684 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.
摘要翻译：本公开提供了一种用于制造存储器件的方法，包括：提供形成在衬底上的多个栅极结构，其中栅极结构包括设置在栅极结构的顶部上的覆盖层，并且每个两个相邻的栅极结构由一个沟; 在基底上覆盖地形成多晶硅层以填补间隙; 对多晶硅层进行平坦化处理，获得多晶硅插塞; 并且在平坦化处理之后进行氧化处理，将多晶硅插塞的一部分和栅极结构上的剩余多晶硅层转换成氧化硅。

99. 发明申请

US20120302049A1 METHOD FOR IMPLANTING WAFER 审中-公开
标题翻译：埋植方法
公开(公告)号：US20120302049A1
公开(公告)日：2012-11-29
申请号：US13115030
申请日：2011-05-24
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/265
CPC分类号： H01L21/26513
摘要： The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different.
摘要翻译：本公开提供了一种用于晶片植入的方法，包括以下步骤：提供晶片，其中晶片包括中心圆形部分和与晶片边缘相邻的外围环形部分，并且其中中心圆形部分和周边环形部分是同心的以及将离子束注入到所述晶片中，其中所述中心圆形部分具有第一平均植入剂量，并且所述周边环形部分具有第二平均植入剂量，并且所述第一平均植入剂量和所述第二平均植入剂量是不同的。

100. 发明申请

US20120299185A1 Slit Recess Channel Gate and Method of Forming the Same 有权
标题翻译：狭缝凹槽通道门及其形成方法
公开(公告)号：US20120299185A1
公开(公告)日：2012-11-29
申请号：US13117162
申请日：2011-05-27
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/4236 , H01L21/28114 , H01L21/76224 , H01L29/42376 , H01L29/4966 , H01L29/66553
摘要： A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.
摘要翻译：还设置狭缝凹槽通道门。狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。衬底具有第一沟槽。栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。本发明还提供了形成狭缝凹槽通道浇口的方法。

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