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1. 发明申请

US20130052820A1 METHOD OF FORMING CONDUCTIVE PATTERN 有权
标题翻译：形成导电图案的方法
公开(公告)号：US20130052820A1
公开(公告)日：2013-02-28
申请号：US13214244
申请日：2011-08-22
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/28
CPC分类号： H01L21/321 , H01L21/76856 , H01L21/76861 , H01L21/76876 , H01L21/76885
摘要： A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.
摘要翻译：提供形成导电图案的方法。在底层上形成接种层。通过使用能量射线，对接种层的表面的一部分进行照射处理。因此，接种层包括多个照射区域和多个未照射区域。对接种层的照射区域进行转化处理。进行选择性生长处理，以在接种层的每个未照射区域上形成导电图案。去除接种层的照射区域，使得导电图案彼此绝缘。

2. 发明授权

US08536056B2 Method of forming conductive pattern 有权
标题翻译：形成导电图案的方法
公开(公告)号：US08536056B2
公开(公告)日：2013-09-17
申请号：US13214244
申请日：2011-08-22
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/28
CPC分类号： H01L21/321 , H01L21/76856 , H01L21/76861 , H01L21/76876 , H01L21/76885
摘要： A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.
摘要翻译：提供形成导电图案的方法。在底层上形成接种层。通过使用能量射线，对接种层的表面的一部分进行照射处理。因此，接种层包括多个照射区域和多个未照射区域。对接种层的照射区域进行转化处理。进行选择性生长处理，以在接种层的每个未照射区域上形成导电图案。去除接种层的照射区域，使得导电图案彼此绝缘。

3. 发明授权

US08410535B2 Capacitor and manufacturing method thereof 有权
标题翻译：电容器及其制造方法
公开(公告)号：US08410535B2
公开(公告)日：2013-04-02
申请号：US13093840
申请日：2011-04-25
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L27/108 , H01L29/76 , H01L21/8242
CPC分类号： H01L28/75
摘要： A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.
摘要翻译：提供电容器及其制造方法。电容器包括第一电极，第一金属层，电介质层和第二电极。第一电极设置在基板上。第一金属层设置在第一电极上。电介质层设置在第一金属层上，其中第一金属层的材料不与电介质层的材料反应。第二电极设置在电介质层上。

4. 发明申请

US20130071978A1 FABRICATING METHOD OF TRANSISTOR 有权
标题翻译：晶体管的制作方法
公开(公告)号：US20130071978A1
公开(公告)日：2013-03-21
申请号：US13236656
申请日：2011-09-20
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/66606 , H01L21/28044 , H01L29/66553 , H01L29/78
摘要： A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.
摘要翻译：提供晶体管的制造方法。图案化的牺牲层形成在衬底上，其中图案化牺牲层包括暴露衬底的多个开口。通过使用图案化牺牲层作为掩模，在衬底上进行掺杂工艺，从而在由开口暴露的衬底中形成掺杂源极区域和掺杂漏极区域。执行选择性生长工艺以在掺杂源极区域和掺杂漏极区域上分别形成源极和漏极。去除图案化牺牲层以暴露源极和漏极之间的衬底。栅极形成在源极和漏极之间的衬底上。

5. 发明申请

US20120270411A1 MANUFACTURING METHOD OF GATE DIELECTRIC LAYER 审中-公开
标题翻译：门电介质层的制造方法
公开(公告)号：US20120270411A1
公开(公告)日：2012-10-25
申请号：US13092994
申请日：2011-04-25
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/316
CPC分类号： H01L21/28229 , H01L29/518
摘要： A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N2 and O2, where the temperature of the annealing treatment is 900° C. to 950° C., the pressure of the annealing treatment is 5 Torr to 10 Torr, and the content ratio of the N2 to O2 is 0.5 to 0.8.
摘要翻译：提供了栅介质层的制造方法。进行氧化处理以在基板上形成氧化物层。进行氮化处理以在氧化物层上形成氮化物层。在N2和O2的混合气体中进行退火处理，其中退火处理的温度为900℃至950℃，退火处理的压力为5托至10托，并且含量比 N 2至O 2为0.5至0.8。

6. 发明授权

US08772119B2 Fabricating method of transistor 有权
标题翻译：晶体管的制造方法
公开(公告)号：US08772119B2
公开(公告)日：2014-07-08
申请号：US13236656
申请日：2011-09-20
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/66606 , H01L21/28044 , H01L29/66553 , H01L29/78
摘要： A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.
摘要翻译：提供晶体管的制造方法。图案化的牺牲层形成在衬底上，其中图案化牺牲层包括暴露衬底的多个开口。通过使用图案化牺牲层作为掩模，在衬底上进行掺杂工艺，从而在由开口暴露的衬底中形成掺杂源极区域和掺杂漏极区域。执行选择性生长工艺以在掺杂源极区域和掺杂漏极区域上分别形成源极和漏极。去除图案化牺牲层以暴露源极和漏极之间的衬底。在源极和漏极之间的衬底上形成栅极。

7. 发明申请

US20130071992A1 SEMICONDUCTOR PROCESS 审中-公开
标题翻译：半导体工艺
公开(公告)号：US20130071992A1
公开(公告)日：2013-03-21
申请号：US13237975
申请日：2011-09-21
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/762
CPC分类号： H01L21/762 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02664
摘要： A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer.
摘要翻译：提供半导体工艺。绝缘层形成在半导体衬底上。去除绝缘层的一部分，以便形成多个隔离结构和布置在隔离结构之间并露出半导体衬底的网孔。通过进行选择性生长处理，从由网眼露出的半导体衬底的表面形成半导体层，使得隔离结构设置在半导体层中。

8. 发明申请

US20120270408A1 MANUFACTURING METHOD OF GATE DIELECTRIC LAYER 审中-公开
标题翻译：门电介质层的制造方法
公开(公告)号：US20120270408A1
公开(公告)日：2012-10-25
申请号：US13093838
申请日：2011-04-25
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/31
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518
摘要： A manufacturing method of a gate dielectric layer that includes a nitride layer and an oxide layer is provided. A substrate is provided. A nitridation treatment is performed to form the nitride layer on the substrate. An oxidation treatment is performed subsequent to the formation of the nitride layer to form the oxide layer between the nitride layer and the substrate.
摘要翻译：提供了包括氮化物层和氧化物层的栅极电介质层的制造方法。提供基板。进行氮化处理以在衬底上形成氮化物层。在形成氮化物层之后进行氧化处理，以在氮化物层和衬底之间形成氧化物层。

9. 发明申请

US20120267760A1 CAPACITOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：电容器及其制造方法
公开(公告)号：US20120267760A1
公开(公告)日：2012-10-25
申请号：US13093840
申请日：2011-04-25
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/75
摘要： A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.
摘要翻译：提供电容器及其制造方法。电容器包括第一电极，第一金属层，电介质层和第二电极。第一电极设置在基板上。第一金属层设置在第一电极上。电介质层设置在第一金属层上，其中第一金属层的材料不与电介质层的材料反应。第二电极设置在电介质层上。

10. 发明授权

US07022603B2 Method for fabricating semiconductor device having stacked-gate structure 有权
标题翻译：具有层叠栅结构的半导体器件的制造方法
公开(公告)号：US07022603B2
公开(公告)日：2006-04-04
申请号：US10683612
申请日：2003-10-10
申请人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
发明人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
IPC分类号： H01L21/44
CPC分类号： H01L21/28052 , H01L29/4933
摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.
摘要翻译：一种半导体制造方法，该半导体器件具有堆叠栅极结构。通过介电层与衬底绝缘的衬底上形成多晶硅层。在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。使用氮气和氢气对氮化钨层进行退火。依次形成覆盖氮化钨层的钨层和覆盖层。

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