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91. 发明授权

US07932506B2 Fully self-aligned pore-type memory cell having diode access device 有权
标题翻译：具有二极管接入装置的全自对准孔型存储单元
公开(公告)号：US07932506B2
公开(公告)日：2011-04-26
申请号：US12177533
申请日：2008-07-22
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1683 , Y10S438/90
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括多个存储器单元。多个存储单元中的每个存储器单元包括二极管，其包括掺杂半导体材料和二极管上的电介质间隔物，并且限定开口，所述电介质间隔物具有与二极管的侧面自对准的侧面。每个存储单元还包括介质间隔物上的存储元件，并且包括开口内接触二极管顶表面的部分。

92. 发明申请

US20100254425A1 PHASE CHANGE MATERIAL BASED TEMPERATURE SENSOR 有权
标题翻译：基于相变材料的温度传感器
公开(公告)号：US20100254425A1
公开(公告)日：2010-10-07
申请号：US12819721
申请日：2010-06-21
申请人： Nazmul Habib , Chung Hon Lam , Robert McMahon
发明人： Nazmul Habib , Chung Hon Lam , Robert McMahon
IPC分类号： G01N25/02
CPC分类号： G01K11/06 , G01K7/16 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation.
摘要翻译：位于半导体芯片中的相变材料块被重置为非晶态。相变材料块可以连接到可以以模拟输出格式或数字输出格式将测量的电阻数据传输到输入/输出焊盘的内部电阻测量电路。根据环境温度，相变材料块的电阻变化。通过测量与校准温度下的相变材料的电阻相比的分数电阻变化，可以精确地测量相变材料周围的区域的温度。可以在内部电阻测量电路和输入/输出焊盘之间采用逻辑解码器和输入/输出电路。可以在半导体芯片中采用包含相变材料块的多个温度检测电路，以便在芯片操作期间能够进行精确的温度分布。

93. 发明授权

US07791057B2 Memory cell having a buried phase change region and method for fabricating the same 有权
标题翻译：具有埋置相变区的存储单元及其制造方法
公开(公告)号：US07791057B2
公开(公告)日：2010-09-07
申请号：US12107573
申请日：2008-04-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro G. Schrott
发明人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro G. Schrott
IPC分类号： H01L29/02
CPC分类号： H01L45/143 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1666
摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.
摘要翻译：描述存储单元以及制造方法。本文所述的存储单元包括底部电极，其包括基部和基部上的柱部，所述柱部的宽度小于基部的宽度。电介质围绕底部电极并具有顶部表面。存储元件覆盖在底部电极上并且包括从电介质的顶表面延伸以与底部电极的柱部分接触的凹部，其中存储元件的凹部具有基本上等于柱的宽度的宽度部分底部电极。顶部电极位于存储元件上。

94. 发明申请

US20100193763A1 CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE 有权
标题翻译：当前的相位变化记忆元素结构
公开(公告)号：US20100193763A1
公开(公告)日：2010-08-05
申请号：US12727672
申请日：2010-03-19
申请人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
发明人： Chieh-Fang Chen , Shih Hung Chen , Yi-Chou Chen , Thomas Happ , Chia Hua Ho , Ming-Hsiang Hsueh , Chung Hon Lam , Hsiang-Lan Lung , Jan Boris Philipp , Simone Raoux
IPC分类号： H01L45/00
CPC分类号： B82Y10/00 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
摘要翻译：使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝缘体层形成电流收缩层的硬掩模。纳米颗粒优选在下面的表面上自对准和/或自平坦化。电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电材料。电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

95. 发明授权

US07579611B2 Nonvolatile memory cell comprising a chalcogenide and a transition metal oxide 有权
标题翻译：包含硫族化物和过渡金属氧化物的非挥发性存储单元
公开(公告)号：US07579611B2
公开(公告)日：2009-08-25
申请号：US11353419
申请日：2006-02-14
申请人： Chung Hon Lam , Gerhard Ingmar Meijer , Alejandro Gabriel Schrott
发明人： Chung Hon Lam , Gerhard Ingmar Meijer , Alejandro Gabriel Schrott
IPC分类号： H01L29/12 , G11C11/00 , G11C11/56
CPC分类号： H01L45/145 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C2213/32 , H01L45/04
摘要： A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.
摘要翻译：用于集成电路的存储单元包括硫族化物特征和过渡金属氧化物特征。硫族化物特征和过渡金属氧化物特征都具有至少两个稳定的电阻状态。通过将硫族化物特征置于其稳定的电阻状态之一并且将过渡金属氧化物特征置于其稳定的电阻状态之一中，可将至少两位数据同时存储在存储单元中。

96. 发明申请

US20090065761A1 PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES IN BEOL REGIONS USING EXTERNALLY HEATED PHASE CHANGE MATERIAL 有权
标题翻译：使用外部加热相变材料在BEOL区域可编程保险丝/非易失性存储器结构
公开(公告)号：US20090065761A1
公开(公告)日：2009-03-12
申请号：US11850742
申请日：2007-09-06
申请人： Kuang-Neng Chen , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Chung Hon Lam , Lia Krusin-Elbaum , Dennis M. Newns , Byeongju Park , Sampath Purushothaman
发明人： Kuang-Neng Chen , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Chung Hon Lam , Lia Krusin-Elbaum , Dennis M. Newns , Byeongju Park , Sampath Purushothaman
IPC分类号： H01L47/00 , H01L21/82
CPC分类号： H01L23/5256 , H01L27/2436 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.
摘要翻译：可编程相变材料（PCM）结构包括形成在半导体器件的BEOL级的加热器元件，BEOL级包括其中的低K电介质材料; 与加热器元件的第一端电接触的第一通孔和与加热器元件的第二端电接触的第二通孔，从而限定通过第一通孔，加热元件和第二通孔的编程电流通路通过; 设置在所述加热器元件上方的PCM元件，所述PCM元件被配置为通过使用通过所述加热器元件的编程电流在较低电阻结晶状态和较高电阻非晶态之间被编程; 以及与PCM元件电接触的第三通孔，从而限定穿过第三通孔，PCM元件，加热器元件和第二通孔的感测电流路径。

97. 发明授权

US07488967B2 Structure for confining the switching current in phase memory (PCM) cells 失效
标题翻译：将开关电流限制在相位存储器（PCM）单元中的结构
公开(公告)号：US07488967B2
公开(公告)日：2009-02-10
申请号：US11100312
申请日：2005-04-06
申请人： Geoffrey W. Burr , Chung Hon Lam , Simone Raoux , Stephen M. Rossnagel , Alejandro G. Schrott , Jonathan Z. Sun , Hemantha K. Wickramasinghe
发明人： Geoffrey W. Burr , Chung Hon Lam , Simone Raoux , Stephen M. Rossnagel , Alejandro G. Schrott , Jonathan Z. Sun , Hemantha K. Wickramasinghe
IPC分类号： H01L29/02
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： Disclosed are a phase change memory cell and a method of forming the memory cell. The memory cell comprises a main body of phase change material connected directly to a bottom contact and via a narrow channel of phase change material to a top contact. The channel is tapered from the top contact towards the main body. A minimum width of the channel has a less than minimum lithographic dimension and is narrower than a width of the main body. Therefore, the channel provides a confined region for the switching current path and restricts phase changing to within the channel. In addition an embodiment of the memory cell isolates the main body of phase change material by providing a space between the phase change material and the cell walls. The space allows the phase change material to expand and contract and also limits heat dissipation.
摘要翻译：公开了相变存储单元和形成存储单元的方法。存储单元包括相变材料的主体，其直接连接到底部触点，并经由相位改变材料的窄通道连接到顶部触点。通道从顶部触点向主体逐渐变细。通道的最小宽度具有小于最小光刻尺寸，并且窄于主体的宽度。因此，该通道为开关电流路径提供一个限制区域，并将相位变化限制在通道内。此外，存储器单元的实施例通过在相变材料和单元壁之间提供空间来隔离相变材料的主体。该空间允许相变材料膨胀和收缩，并且还限制了散热。

98. 发明授权

US07473921B2 Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement 失效
标题翻译：具有同心相变材料的非易失性存储单元围绕柱布置形成
公开(公告)号：US07473921B2
公开(公告)日：2009-01-06
申请号：US11448549
申请日：2006-06-07
申请人： Chung Hon Lam , Alejandro Gabriel Schrott
发明人： Chung Hon Lam , Alejandro Gabriel Schrott
IPC分类号： H01L47/00
CPC分类号： H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1691
摘要： A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.
摘要翻译：存储单元包括第一特征和第二特征。第二特征包括介电材料并限定至少部分地覆盖第一特征的开口。在第一特征上形成第三特征并且部分地填充第二特征中的开口。此外，相变材料至少填充第二特征和第三特征之间的体积。响应于将切换信号施加到存储器单元，相变材料的至少一部分可操作以在较低和较高的电阻状态之间切换。

99. 发明申请

US20080244370A1 MULTI-BIT MEMORY ERROR DETECTION AND CORRECTION SYSTEM AND METHOD 有权
标题翻译：多位存储器错误检测和校正系统及方法
公开(公告)号：US20080244370A1
公开(公告)日：2008-10-02
申请号：US11694025
申请日：2007-03-30
申请人： Chung Hon Lam
发明人： Chung Hon Lam
IPC分类号： G06F11/10
CPC分类号： G06F11/1072 , G11C11/56 , G11C11/5621 , G11C11/5678 , G11C13/0004 , G11C27/005 , G11C29/00 , G11C2211/5641
摘要： A system and method for operating a collection of memory cells includes storing binary data values and parity data values by associating binary values with a common adjustable characteristic parameter of a memory cell collection. Probability distribution functions for values of the characteristic parameter of the memory cell collection are read and constructed. Binary data values and parity data values stored in the memory cell collection are retrieved. Parity data for error detection and error correction is evaluated in the binary data values.
摘要翻译：用于操作存储器单元的集合的系统和方法包括通过将二进制值与存储器单元集合的公共可调特性参数相关联来存储二进制数据值和奇偶校验数据值。对存储单元集合的特性参数的值的概率分布函数进行读取和构造。检索存储在存储单元集合中的二进制数据值和奇偶校验数据值。用于错误检测和纠错的奇偶校验数据在二进制数据值中进行评估。

100. 发明申请

US20080157051A1 Nonvolatile Memory Cell with Concentric Phase Change Material Formed Around a Pillar Arrangement 有权
标题翻译：具有同心相变材料的非易失性存储单元围绕支柱布置形成
公开(公告)号：US20080157051A1
公开(公告)日：2008-07-03
申请号：US12051389
申请日：2008-03-19
申请人： Chung Hon Lam , Alejandro Gabriel Schrott
发明人： Chung Hon Lam , Alejandro Gabriel Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1691
摘要： A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.
摘要翻译：存储单元包括第一特征和第二特征。第二特征包括介电材料并限定至少部分地覆盖第一特征的开口。在第一特征上形成第三特征并且部分地填充第二特征中的开口。此外，相变材料至少填充第二特征和第三特征之间的体积。响应于将切换信号施加到存储器单元，相变材料的至少一部分可操作以在较低和较高的电阻状态之间切换。

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