专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明专利

JP2010267655A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010267655A
公开(公告)日：2010-11-25
申请号：JP2009115502
申请日：2009-05-12
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO , NARASAKI ATSUSHI , FUJII RYOICHI
IPC分类号： H01L29/861 , H01L29/06 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/872
CPC分类号： H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1608 , H01L29/408 , H01L29/7811 , H01L29/8611 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device using a guard ring, which secures desired withstand voltage characteristics even when a foreign matter or the like sticks on the surface of a conductive film. SOLUTION: The semiconductor device is provided with a p-type guard ring region 7 surrounding a pn junction region 8, an insulating film 9 covering the p-type guard ring region 7, the conductive film 11 electrically connected to the p-type guard ring region 7 through a contact hole 10 provided to the insulating film 9, and a semi-insulating film 12 covering the insulating film 9 and conductive film 11. Further, the conductive film 11 is intermittently provided. Consequently, even when the foreign matter or the like sticks on the surface of the conductive film 11, the desired withstand voltage characteristics can be secured. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种使用保护环的半导体器件，其即使当异物等粘附在导电膜的表面上时也能够确保期望的耐电压特性。解决方案：半导体器件设置有围绕pn结区域8的p型保护环区域7，覆盖p型保护环区域7的绝缘膜9，电连接到p型保护环区域7的导电膜11。通过设置在绝缘膜9上的接触孔10形成防护环区域7，覆盖绝缘膜9和导电膜11的半绝缘膜12.此外，间断地设置导电膜11。因此，即使当异物等粘附在导电膜11的表面上时，也可以确保期望的耐电压特性。版权所有（C）2011，JPO＆INPIT

92. 发明专利

JP2010239152A Silicon carbide semiconductor device 审中-公开
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2010239152A
公开(公告)日：2010-10-21
申请号：JP2010143030
申请日：2010-06-23
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： WATANABE TOMOKATSU , AYA ATSUSHI , MIURA NARIHISA , SAKAI KEIKO , YOSHIDA SHOHEI , TANIOKA HISAKAZU , NAKAO YUKIYASU , TARUI YOICHIRO , IMAIZUMI MASAYUKI
IPC分类号： H01L21/28 , H01L21/336 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which is free of a process defect in manufacturing of the device and has a p-type base ohmic contact of low resistance.
SOLUTION: In an ion implantation process, a silicon carbide wafer is held at a temperature of 175 to 300°C, preferably, 175 to 200°C. Resistivity of a p-type base ohmic contact using a p++ region formed by ion implantation at 175 to 300°C is 8E-4 Ωcm
2 or less, and less than that when ion implantation is carried out at a temperature of >300°C. Further, no process defect is caused.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种在制造装置中没有工艺缺陷并具有低电阻的p型基极欧姆接触的碳化硅半导体器件。解决方案：在离子注入工艺中，碳化硅晶片保持在175至300℃，优选175至200℃的温度。使用在175〜300℃的离子注入形成的p ++区域的p型基极欧姆接触的电阻率为8E-4Ω·cm·SP·2以下，小于在离子注入时温度> 300°C。此外，不会引起工艺缺陷。版权所有（C）2011，JPO＆INPIT

93. 发明专利

JP2009130244A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009130244A
公开(公告)日：2009-06-11
申请号：JP2007305586
申请日：2007-11-27
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： WATANABE HIROSHI , YUYA NAOKI , OTSUKA KENICHI , MIURA NARIHISA , TARUI YOICHIRO
IPC分类号： H01L29/78 , H01L21/28 , H01L29/12 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To reduce channel resistance in a vertical semiconductor device wherein a p-type source contact part is disposed in a p-type semiconductor region of a cell corner part.
SOLUTION: The semiconductor device has: a p-type bridge layer 12 which is disposed in a surface layer part of an n
- type drift layer 2 and connects a p-type base layer 3; an n
+ type conductive layer 14 which is formed apart from a p-type source layer 4 by a second distance in a marginal part of the p-type bridge layer 12; and a p
+ type contact layer 13 enclosed with the n
+ type conductive layer 14. It also has: a channel region between the n
+ type source layer 4 and the n
- type drift layer 2; and a gate electrode 6 formed in a channel region between the n
+ type source layer 4 and the n
+ type conductive layer 14 via a gate insulating film 5. The p
+ type contact layer 13 is formed deeper than the n
+ type conductive layer 14 and shallower than the p-type bridge layer 12. The n
+ type conductive layer 14 is constituted in continuity with the n
- type drift layer 2.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了降低其中p型源极接触部分设置在电池角部分的p型半导体区域中的垂直半导体器件中的沟道电阻。解决方案：半导体器件具有：p型桥接层12，其设置在n型SP型漂移层2的表层部分中，并连接p型基极层3; 在p型桥接层12的边缘部分中与p型源极层4隔开第二距离形成的n + 型导电层14; 以及由n + 型导电层14包围的ap + 型接触层13.它还具有：n + 型之间的沟道区源层4和n - / SP>型漂移层2; 以及通过栅极绝缘膜5形成在n + SP型源极层4和n + / SP>型导电层14之间的沟道区域中的栅电极6。 SP> + 型接触层13形成得比n型SP + + / SP型导电层14深，并且比p型桥接层12浅。型导电层14与n - SP型漂移层2连续地构成。版权所有（C）2009，JPO＆INPIT

94. 发明专利

JP2008243900A Silicon carbide semiconductor device and manufacturing method thereof 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2008243900A
公开(公告)日：2008-10-09
申请号：JP2007078634
申请日：2007-03-26
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SAWADA TAKAO , TARUI YOICHIRO
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L29/12 , H01L29/78
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device, along with its manufacturing method, capable of increasing the number of CNTs by enlarging the surface area of a catalyst layer and a formation condition of a thin film which sufficiently functions as a catalyst for forming the CNT, having an ohmic contact even after hot heat treatment after contact layer formation. SOLUTION: The manufacturing method of a silicon carbide semiconductor device includes a process (a) in which an impurity is introduced into the surface of an SiC 1, a process (b) in which after introduction of impurity, the surface of SiC 1 is annealed to form a rough part 4 on the surface of SiC 1, and a process (c) in which with the surface of the rough part 4 of the SiC 1 as a base material, CNT 7 is formed thereon. The number of CNT 7 is increased by enlarging the surface area of a contact electrode layer 5. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种碳化硅半导体器件及其制造方法，能够通过扩大催化剂层的表面积和充分发挥作用的催化剂层的形成条件来增加CNT的数量用于形成CNT的催化剂，即使在接触层形成后的热热处理之后也具有欧姆接触。解决方案：碳化硅半导体器件的制造方法包括其中将杂质引入SiC 1的表面的工艺（a），其中在引入杂质之后，SiC的表面的工艺（b） 1在SiC 1的表面上进行退火以形成粗糙部分4，其中以SiC 1的粗糙部分4的表面为基材的方法（c）形成CNT 7。通过扩大接触电极层5的表面积来增加CNT 7的数量。版权所有：（C）2009，JPO＆INPIT

95. 发明专利

JP2007280978A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007280978A
公开(公告)日：2007-10-25
申请号：JP2006101386
申请日：2006-04-03
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO , YUYA NAOKI , WATANABE HIROSHI
IPC分类号： H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of preventing an alignment mark used for overlapping in a manufacturing process from being deformed asymmetrically in a heat-treatment process, such as activation annealing treatment and epitaxial growth in a manufacturing process in the semiconductor device using SiC for a substrate.
SOLUTION: The method for manufacturing the semiconductor device using SiC for the substrate comprises: a process for forming an alignment mark 2 on a {0001} plane in the SiC substrate 1; and a process for forming a prescribed pattern on the SiC substrate 1 by aligning a transfer mask and the SiC substrate 1, based on the alignment mark 2.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，该半导体器件能够防止在制造工艺中用于重叠的对准标记在热处理工艺中不对称地变形，例如激活退火处理和外延生长在使用SiC用于衬底的半导体器件中的制造工艺。解决方案：用于制造使用SiC的半导体器件用于衬底的方法包括：在SiC衬底1中的ä0001}面上形成对准标记2的工艺; 以及通过基于对准标记2对转印掩模和SiC基板1在SiC基板1上形成规定图案的工序。（C）2008，JPO＆INPIT

96. 发明专利

JP2007273727A Alignment mark, and forming method therefor, and semiconductor device and manufacturing method therefor 有权
标题翻译：对准标记及其形成方法及其半导体器件及其制造方法
公开(公告)号：JP2007273727A
公开(公告)日：2007-10-18
申请号：JP2006097553
申请日：2006-03-31
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： WATANABE HIROSHI , YUYA NAOKI , TARUI YOICHIRO
IPC分类号： H01L21/027
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an alignment mark that is restrained in deterioration of positioning accuracy, even after passage of an epitaxial film deposition process and high-temperature annealing process.
SOLUTION: The alignment mark 14 is formed by a stepwise step difference pattern in a cross-sectional shape. The step difference pattern includes a first step difference pattern 11, formed by digging down a principal surface of a substrate 2; and a second step difference pattern 13, formed by further digging down the principal surface of the substrate 2, in continuation with the first step difference pattern 11 below the first step difference pattern 11 formed by digging down the principal surface of the substrate 2. A sidewall part 17 of the first step difference pattern 11 and a sidewall part 18 of the second step difference pattern 13 are formed at the same angle and is formed so as to have the same crystal orientation.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使在通过外延膜沉积工艺和高温退火工艺之后，也提供限定在定位精度降低的对准标记。解决方案：对准标记14由横截面形状的逐步阶差分图形形成。台阶差分图案包括通过挖掘基板2的主表面而形成的第一阶差分图案11; 以及通过进一步向下挖掘基板2的主表面而形成的第二阶梯差异图案13，其与通过挖掘基板2的主表面而形成的第一阶梯差异图案11之下的第一阶梯差异图案11连续。第一台阶差异图案11的侧壁部17和第二台阶差异图案13的侧壁部18以相同的角度形成，并且形成为具有相同的晶体取向。版权所有（C）2008，JPO＆INPIT

97. 发明专利

JP2007227949A Manufacturing method of semiconductor device comprising horizontal high breakdown voltage element 有权
标题翻译：包含水平高电压突变元件的半导体器件的制造方法
公开(公告)号：JP2007227949A
公开(公告)日：2007-09-06
申请号：JP2007088721
申请日：2007-03-29
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： AKIYAMA HAJIME , TARUI YOICHIRO
IPC分类号： H01L29/861 , H01L21/02 , H01L21/265 , H01L27/12 , H01L29/06 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device comprising a horizontal high breakdown voltage element having an extremely high breakdown voltage which is not restricted by electric field concentration of an SOI layer surface. SOLUTION: In the method for manufacturing the semiconductor device comprising the horizontal high breakdown voltage element, an SiC thin film layer 20 made of a material which has a wide band gap wider than that of a material of a semiconductor layer 2 by introducing impurities into the semiconductor layer 2 is formed. A buried insulating layer 3 and a silicon substrate 1 are laminated to the semiconductor layer 2 having the SiC thin film layer 20. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，其包括不受SOI层表面的电场浓度限制的具有极高耐击穿电压的水平高击穿电压元件。解决方案：在包括水平高击穿电压元件的半导体器件的制造方法中，SiC薄膜层20由具有比半导体层2的材料宽的宽的带隙的材料制成，通过引入形成了半导体层2中的杂质。掩埋绝缘层3和硅衬底1层压到具有SiC薄膜层20的半导体层2上。（C）2007，JPO＆INPIT

98. 发明专利

JP2004319815A Semiconductor device 有权
公开(公告)号：JP2004319815A
公开(公告)日：2004-11-11
申请号：JP2003112592
申请日：2003-04-17
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , TARUI YOICHIRO , IMAIZUMI MASAYUKI , SUGIMOTO HIROSHI , TAKAMI TETSUYA
IPC分类号： H01L29/78 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device having a high withstand voltage, a low on-resistance, and hard to deteriorate an element characteristic.
SOLUTION: The semiconductor device comprises an n-type substrate 1, an n-type drift layer 2 formed on the n-type substrate 1, first and second n-type semiconductor layers 3, 4, a plurality of p-type base regions 5 separated from one another at predetermined intervals, an n-type source region 6 formed in each base region 5, a source electrode 10 provided on the surface of a part of each source region 6, and a gate electrode 8 provided on the surface of a part of each source region 6 and on the surface of the second semiconductor layer 4 between the source regions 6 through the gate insulating film. The first and the second semiconductor layers 3, 4 are crystal layers formed by epitaxial growth. A relation among the impurity concentration N
1 of the drift layer 2, the impurity concentration N
2 of the first semiconductor layer 3, and the impurity concentration N
3 of the second semiconductor layer 4 is shown by N
3 1 2 .
COPYRIGHT: (C)2005,JPO&NCIPI

99. 发明专利

JP2003229565A SEMICONDUCTOR ELEMENT AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003229565A
公开(公告)日：2003-08-15
申请号：JP2002027014
申请日：2002-02-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUGIMOTO HIROSHI , OTSUKA KENICHI , TARUI YOICHIRO , MATSUNO YOSHINORI
IPC分类号： H01L21/28 , H01L29/41 , H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element which contains a forming process of an electrode in which process thermal treatment using heating due to light irradiation is performed and in which element semiconductor material having a forbidden band wider than that of silicon is used as a substrate, and heating temperature distribution of the semiconductor element in the light irradiation thermal treatment is made uniform, and to provide a method for manufacturing the semiconductor element. SOLUTION: In a forming process of an ohmic electrode, the electrode is formed in such a manner that a part in which electrode metal exists and a part in which the electrode metal does not exist are mixed on one surface of the substrate. The substrate is arranged on a testpiece holding table of light irradiation and heating equipment which table is used for holding and heating a testpiece to be heated, and light irradiation is performed. COPYRIGHT: (C)2003,JPO

100. 发明专利

JP2003069049A Semiconductor and manufacturing method thereof 审中-公开
标题翻译：半导体及其制造方法
公开(公告)号：JP2003069049A
公开(公告)日：2003-03-07
申请号：JP2001252529
申请日：2001-08-23
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , TARUI YOICHIRO , IMAIZUMI MASAYUKI , SUGIMOTO HIROSHI
IPC分类号： H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is improved so that high- performance element characteristics can be achieved in simple manufacturing process.
SOLUTION: A metal electrode 12 is provided on a semiconductor region 2. A resistance layer 3 whose thickness and resistivity are less than 10 nm and 100 Ω/cm or more, respectively, is provided on the semiconductor region 2 and at the same time at least around a metal electrode 12. The semiconductor region 2 that becomes an operation region is covered with the resistance layer 3 of a highly pure epitaxial growth layer, thus preventing generation of defects and levels, and hence achieving apparatus characteristics that are estimated according to the semiconductor region 2.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种改进的半导体器件，以便在简单的制造工艺中可以实现高性能元件特性。解决方案：在半导体区域2上设置金属电极12.在半导体区域2上设置厚度和电阻率分别小于10nm和100Ω/ cm以上的电阻层3，同时在最少在金属电极12周围。成为操作区域的半导体区域2被高纯度外延生长层的电阻层3覆盖，从而防止缺陷和电平的产生，从而实现根据半导体区域2。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式