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91. 发明申请

US20120038008A1 Field Effect Transistor Device with Self-Aligned Junction and Spacer 审中-公开
标题翻译：具有自对准结和间隔的场效应晶体管器件
公开(公告)号：US20120038008A1
公开(公告)日：2012-02-16
申请号：US12857017
申请日：2010-08-16
申请人： Dechao Guo , Pranita Kulkarni , Ramachandran Muralidhar , Chun-Chen Yeh
发明人： Dechao Guo , Pranita Kulkarni , Ramachandran Muralidhar , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7834
摘要： In one aspect of the present invention, a method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, forming an ion doped drain extension portion in the substrate, forming a first spacer portion adjacent to the dummy gate stack, removing the dummy gate stack to expose a channel region of the substrate, a portion of the ion doped source extension portion, and a portion of the ion doped drain extension portion, forming a second spacer portion on the exposed portion of the ion doped source extension portion and on the exposed portion of the ion doped drain extension portion, and forming a gate stack on the exposed channel region of the substrate.
摘要翻译：在本发明的一个方面中，一种用于制造场效应晶体管器件的方法包括在衬底的第一部分上形成虚拟栅叠层，形成与虚栅极堆叠相邻的源区和漏区，形成离子掺杂源极延伸部分，在衬底中形成离子掺杂的漏极延伸部分，形成与虚拟栅极堆叠相邻的第一间隔部分，去除伪栅极堆叠以暴露衬底的沟道区域，一部分离子掺杂源极延伸部分和离子掺杂漏极延伸部分的一部分，在离子掺杂源极延伸部分的暴露部分上以及在离子掺杂漏极延伸部分的暴露部分上形成第二间隔部分，并形成栅叠层衬底的暴露的沟道区域。

92. 发明申请

US20120038007A1 Field Effect Transistor Device With Self-Aligned Junction 审中-公开
标题翻译：具有自对准结的场效应晶体管器件
公开(公告)号：US20120038007A1
公开(公告)日：2012-02-16
申请号：US12857013
申请日：2010-08-16
申请人： Dechao Guo , Pranita Kulkarni , Ramachandran Muralidhar , Chun-Chen Yeh
发明人： Dechao Guo , Pranita Kulkarni , Ramachandran Muralidhar , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/66537 , H01L29/66575 , H01L29/7833
摘要： A method for fabricating a field effect transistor device includes forming a dummy gate stack on a first portion of a substrate, forming a source region and a drain region adjacent to the dummy gate stack, forming a ion doped source extension portion in the substrate, the source extension portion extending from the source region into the first portion of the substrate, forming an ion doped drain extension portion in the substrate, the drain extension portion extending from the drain region into the first portion of the substrate, removing a portion of the dummy gate stack to expose an interfacial layer of the dummy gate stack, implanting ions in the source extension portion and the drain extension portion to form a channel region in the first portion of the substrate, removing the interfacial layer, and forming a gate stack on the channel region of the substrate.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底的第一部分上形成虚拟栅叠层，形成与虚栅极叠层相邻的源区和漏区，在衬底中形成离子掺杂源延伸部分，源极延伸部分，从源极区域延伸到衬底的第一部分中，在衬底中形成离子掺杂漏极延伸部分，漏极延伸部分从漏极区域延伸到衬底的第一部分中，去除虚部的一部分栅极堆叠以暴露伪栅极堆叠的界面层，在源延伸部分和漏极延伸部分中注入离子，以在衬底的第一部分中形成沟道区域，去除界面层，以及在栅极叠层上形成栅叠层沟道区域。

93. 发明授权

US07947589B2 FinFET formation with a thermal oxide spacer hard mask formed from crystalline silicon layer 有权
标题翻译：由结晶硅层形成的具有热氧化物间隔物硬掩模的FinFET形成
公开(公告)号：US07947589B2
公开(公告)日：2011-05-24
申请号：US12552774
申请日：2009-09-02
申请人： Ramachandran Muralidhar , Marwan H. Khater
发明人： Ramachandran Muralidhar , Marwan H. Khater
IPC分类号： H01L21/3205
CPC分类号： H01L29/66795 , H01L21/3086 , H01L21/845
摘要： A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).
摘要翻译：半导体工艺和装置通过形成通过掩埋绝缘体层（18）与下层第一单晶半导体层（17）隔离的第二单晶半导体层（19）来提供FinFET器件; 图案化和蚀刻第二单晶半导体层（19）以形成具有垂直侧壁的单晶心轴（42）; 热氧化单晶心轴的垂直侧壁以生长具有基本均匀厚度的氧化物间隔物（52）; 选择性地去除所述单晶心轴（42）的任何剩余部分，同时基本上保持所述氧化物间隔物（52）; 以及使用所述氧化物间隔物（52）选择性地蚀刻所述第一单晶半导体层（17）以形成一个或多个FinFET沟道区域（92）。

94. 发明授权

US07361543B2 Method of forming a nanocluster charge storage device 有权
标题翻译：形成纳米团簇电荷存储装置的方法
公开(公告)号：US07361543B2
公开(公告)日：2008-04-22
申请号：US10987047
申请日：2004-11-12
申请人： Robert F. Steimle , Ramachandran Muralidhar , Bruce E. White
发明人： Robert F. Steimle , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L27/11573
摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
摘要翻译：集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。

95. 发明申请

US20070004146A1 Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types 有权
标题翻译：用于集成嵌入式非易失性存储装置的形成与形成多晶体管器件类型的半导体制造工艺
公开(公告)号：US20070004146A1
公开(公告)日：2007-01-04
申请号：US11172728
申请日：2005-07-01
申请人： Erwin Prinz , Ramachandran Muralidhar
发明人： Erwin Prinz , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823857 , Y10S438/962
摘要： A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.
摘要翻译：半导体制造工艺包括在覆盖衬底的第一区域的隧道氧化物上形成多晶硅纳米晶体。沉积第二电介质覆盖在第一区域和第二区域上。在不提供覆盖第一区域中的第二电介质的任何保护层的情况下，进行额外的热氧化步骤而不氧化纳米晶体。然后将栅极电极膜沉积在第二电介质上并被图案化以形成第一和第二栅电极。第二电介质可以是退火的CVD氧化物。额外的热氧化可以包括通过干式氧化形成覆盖在半导体衬底的第三区域上的第三电介质。干燥氧化在第二区域中产生第二电介质下面的界面氧化硅。然后可以暴露基板的第四区域的上表面，并在第四区域的上表面上形成第四电介质。

96. 发明申请

US20060199335A1 Electronic devices including non-volatile memory structures and processes for forming the same 审中-公开
标题翻译：包括非易失性存储器结构的电子设备及其形成工艺
公开(公告)号：US20060199335A1
公开(公告)日：2006-09-07
申请号：US11071977
申请日：2005-03-04
申请人： Rajesh Rao , Ramachandran Muralidhar
发明人： Rajesh Rao , Ramachandran Muralidhar
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/66772
摘要： An electronic device can include an NVM structure and a gate electrode outside an NVM array. In one embodiment, a first gate dielectric layer and a first gate electrode layer are formed before forming NVM cells within an NVM array. The first gate electrode layer helps to protect the first gate dielectric layer from becoming thinner or thicker during subsequent processing used to form NVM cells. In another embodiment, NVM structures and transistor structures can be formed where the NVM structures have one more spacer adjacent to the NVM structures as compared to the transistor structures.
摘要翻译：电子设备可以包括NVM结构和NVM阵列外部的栅电极。在一个实施例中，在形成NVM阵列内的NVM单元之前形成第一栅极介电层和第一栅极电极层。第一栅极电极层有助于在用于形成NVM电池的后续处理期间保护第一栅极介电层变得更薄或更厚。在另一个实施例中，可以形成NVM结构和晶体管结构，其中与晶体管结构相比，NVM结构具有与NVM结构相邻的更多间隔区。

97. 发明申请

US20060030105A1 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US20060030105A1
公开(公告)日：2006-02-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin Prinz , Ramachandran Muralidhar , Rajesh Rao , Michael Sadd , Robert Steimle , Craig Swift , Bruce White
发明人： Erwin Prinz , Ramachandran Muralidhar , Rajesh Rao , Michael Sadd , Robert Steimle , Craig Swift , Bruce White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

98. 发明申请

US20050191808A1 Method for removing nanoclusters from selected regions 失效
标题翻译：从选定区域去除纳米团簇的方法
公开(公告)号：US20050191808A1
公开(公告)日：2005-09-01
申请号：US10787510
申请日：2004-02-26
申请人： Robert Steimle , Jane Yater , Gowrishankar Chindalore , Craig Swift , Steven Anderson , Ramachandran Muralidhar
发明人： Robert Steimle , Jane Yater , Gowrishankar Chindalore , Craig Swift , Steven Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.
摘要翻译：纳米簇被覆盖在集成电路上，然后从不需要纳米团簇的区域去除。在毛毯沉积之前在纳米团簇不需要的那些区域中形成牺牲层。然后去除纳米团簇和牺牲层。在一种形式中，牺牲层包括沉积的含氮化物或含氧化物层。或者，牺牲层包括先前用于在衬底中形成隔离区域的衬垫氧化物或衬垫氮化物层中的至少一个。然后可以将纳米簇装置和非纳群集装置集成到相同的集成电路上。牺牲层的使用保护下层，从而防止随后形成的非纳群集装置的性能下降。

99. 发明授权

US06583057B1 Method of forming a semiconductor device having a layer deposited by varying flow of reactants 失效
标题翻译：形成具有通过改变反应物流而沉积的层的半导体器件的方法
公开(公告)号：US06583057B1
公开(公告)日：2003-06-24
申请号：US09211165
申请日：1998-12-14
申请人： Prasad Alluri , Ramachandran Muralidhar
发明人： Prasad Alluri , Ramachandran Muralidhar
IPC分类号： H01L2100
CPC分类号： C23C16/45523 , C23C16/409 , H01L21/02183 , H01L21/02197 , H01L21/0228 , H01L21/31612
摘要： A method of forming a semiconductor device by placing a semiconductor substrate in a vacuum chamber and subjecting the semiconductor substrate (20) to a sub-atmospheric pressure, and depositing a layer (40) on the semiconductor substrate while maintaining the sub-atmospheric pressure. Deposition of the layer (40) is carried out by sequentially (i) flowing a first reactant into the vacuum chamber at a first flow rate, (ii) reducing flow of the first reactant into the vacuum chamber to a second flow rate, and (iii) increasing flow of the first reactant into the vacuum chamber to a third flow rate.
摘要翻译：通过将半导体衬底放置在真空室中并对半导体衬底（20）施加次大气压力，并且在保持低于大气压力的同时在半导体衬底上沉积层（40）来形成半导体器件的方法。层（40）的沉积通过顺序地（i）以第一流速将第一反应物流入真空室中，（ii）将第一反应物流入真空室中的流量降至第二流量，和 iii）增加第一反应物进入真空室的流量至第三流量。

100. 发明授权

US06320784B1 Memory cell and method for programming thereof 有权
标题翻译：存储单元及其编程方法
公开(公告)号：US06320784B1
公开(公告)日：2001-11-20
申请号：US09524916
申请日：2000-03-14
申请人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
发明人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
IPC分类号： G11C1100
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5671 , G11C16/0416 , G11C2216/08 , H01L29/7887 , H01L29/7888
摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).
摘要翻译：公开了一种存储单元（101），其形成方法和操作。根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。根据替代实施例，存储器单元编程通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现，所述第一电荷可以是来自掺杂的每一个的电子或空穴不连续存储元件（17）。

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