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91. 发明授权

US07557008B2 Method of making a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07557008B2
公开(公告)日：2009-07-07
申请号：US11625882
申请日：2007-01-23
申请人： Rajesh Rao , Ramachandran Muralidhar
发明人： Rajesh Rao , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A method forms a nonvolatile memory device using a semiconductor substrate. A charge storage layer is formed overlying the semiconductor substrate and a layer of gate material is formed overlying the charge storage layer to form a control gate electrode. A protective layer overlies the layer of gate material. Dopants are implanted into the semiconductor substrate and are self-aligned to the control gate electrode on at least one side of the control gate electrode to form a source and a drain in the semiconductor substrate on opposing sides of the control gate electrode. The protective layer prevents the dopants from penetrating into the control gate electrode. The protective layer that overlies the layer of gate material is removed. Electrical contact is made to the control gate electrode, the source and the drain. In one form a select gate is also provided in the memory device.
摘要翻译：一种方法形成使用半导体衬底的非易失性存储器件。形成覆盖在半导体衬底上的电荷存储层，并且形成覆盖电荷存储层的栅极材料层以形成控制栅电极。保护层覆盖栅极材料层。将掺杂剂注入到半导体衬底中，并且在控制栅电极的至少一侧上与控制栅电极自对准，以在控制栅电极的相对侧上的半导体衬底中形成源极和漏极。保护层防止掺杂剂渗入控制栅电极。覆盖栅极材料层的保护层被去除。与控制栅电极，源极和漏极电接触。在一种形式中，选择栅极也被提供在存储器件中。

92. 发明授权

US07528047B2 Self-aligned split gate memory cell and method of forming 有权
标题翻译：自对准分离栅极存储单元及其形成方法
公开(公告)号：US07528047B2
公开(公告)日：2009-05-05
申请号：US11759593
申请日：2007-06-07
申请人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Lakshmanna Vishnubhotla
发明人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Lakshmanna Vishnubhotla
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/42332
摘要： A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.
摘要翻译：使用半导体层形成分离栅极存储器件的方法包括图案化绝缘层以留下其柱。在半导体层上形成栅极电介质。电荷存储层形成在栅极电介质上并沿着柱的第一和第二侧。栅极材料层形成在栅极电介质和支柱上。执行蚀刻以将栅极材料的第一部分横向邻近柱的第一侧并且位于栅极电介质上方的电荷存储层的第一部分上，以用作存储器件的控制栅极，并且栅极材料的第二部分横向邻近柱的第二侧，并且位于栅极电介质上方的电荷存储层的第二部分上，用作选择栅极。

93. 发明授权

US07517747B2 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US07517747B2
公开(公告)日：2009-04-14
申请号：US11530053
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L21/8238
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

94. 发明申请

US20090061608A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SILICON DIOXIDE LAYER 审中-公开
标题翻译：形成具有二氧化硅层的半导体器件的方法
公开(公告)号：US20090061608A1
公开(公告)日：2009-03-05
申请号：US11846633
申请日：2007-08-29
申请人： Tushar P. Merchant , Lakshmanna Vishnubhotla , Ramachandran Muralidhar , Rajesh A. Rao , Sriram Kalpat
发明人： Tushar P. Merchant , Lakshmanna Vishnubhotla , Ramachandran Muralidhar , Rajesh A. Rao , Sriram Kalpat
IPC分类号： H01L21/28
CPC分类号： H01L29/792 , B82Y10/00 , H01L29/40114 , H01L29/42332 , H01L29/66825
摘要： A method of depositing a silicon dioxide layer for a semiconductor device. The method includes depositing the silicon dioxide layer to have a silicon concentration of greater than 30 atomic percent and a nitrogen concentration of less than 5 atomic percent. The depositing includes flowing nitric oxide gas with a silicon precursor over a substrate. In one example, the silicon precursor and nitric oxide are flowed over a substrate with the substrate being at a temperature in a range of approximately 600 to approximately 900 degrees Celsius. In one example, the silicon dioxide layer is formed on a layer including charge storage memory material.
摘要翻译：一种沉积半导体器件的二氧化硅层的方法。该方法包括沉积二氧化硅层以具有大于30原子百分比的硅浓度和小于5原子％的氮浓度。沉积包括在衬底上流动具有硅前体的一氧化氮气体。在一个实例中，硅前体和一氧化氮在衬底上流动，衬底的温度在约600至约900摄氏度的范围内。在一个示例中，二氧化硅层形成在包括电荷存储存储材料的层上。

95. 发明申请

US20080176371A1 METHOD OF MAKING A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080176371A1
公开(公告)日：2008-07-24
申请号：US11625882
申请日：2007-01-23
申请人： Rajesh Rao , Ramachandran Muralidhar
发明人： Rajesh Rao , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A method forms a nonvolatile memory device using a semiconductor substrate. A charge storage layer is formed overlying the semiconductor substrate and a layer of gate material is formed overlying the charge storage layer to form a control gate electrode. A protective layer overlies the layer of gate material. Dopants are implanted into the semiconductor substrate and are self-aligned to the control gate electrode on at least one side of the control gate electrode to form a source and a drain in the semiconductor substrate on opposing sides of the control gate electrode. The protective layer prevents the dopants from penetrating into the control gate electrode. The protective layer that overlies the layer of gate material is removed. Electrical contact is made to the control gate electrode, the source and the drain. In one form a select gate is also provided in the memory device.
摘要翻译：一种方法形成使用半导体衬底的非易失性存储器件。形成覆盖在半导体衬底上的电荷存储层，并且形成覆盖电荷存储层的栅极材料层以形成控制栅电极。保护层覆盖栅极材料层。将掺杂剂注入到半导体衬底中，并且在控制栅电极的至少一侧上与控制栅电极自对准，以在控制栅电极的相对侧上的半导体衬底中形成源极和漏极。保护层防止掺杂剂渗入控制栅电极。覆盖栅极材料层的保护层被去除。与控制栅电极，源极和漏极电接触。在一种形式中，选择栅极也被提供在存储器件中。

96. 发明申请

US20080121967A1 NANOCRYSTAL NON-VOLATILE MEMORY CELL AND METHOD THEREFOR 审中-公开
标题翻译： NANOCRYSTAL非易失性记忆细胞及其方法
公开(公告)号：US20080121967A1
公开(公告)日：2008-05-29
申请号：US11530054
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/40114 , H01L29/513 , H01L29/7881
摘要： A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other, and forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8. The spacing between the plurality of discrete storage elements may be greater than or equal to approximately the thickness of the second dielectric layer.
摘要翻译：形成半导体器件的方法，其优选地是存储单元，包括在半导体衬底上形成第一介电层，在第一介电层上形成多个离散存储元件，其中多个离散存储元件中的每一个具有并且在所述多个分立存储元件上形成第二电介质层，其中所述第二电介质层具有厚度，其中所述第二电介质的厚度与所述直径值的比值小于约0.8。多个离散存储元件之间的间隔可以大于或等于第二电介质层的厚度。

97. 发明授权

US07361567B2 Non-volatile nanocrystal memory and method therefor 有权
标题翻译：非挥发性纳米晶体记忆及其方法
公开(公告)号：US07361567B2
公开(公告)日：2008-04-22
申请号：US11043826
申请日：2005-01-26
申请人： Rajesh A. Rao , Ramachandran Muralidhar , Bruce E. White
发明人： Rajesh A. Rao , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L21/331 , H01L21/20 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： H01L29/42348 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518
摘要： A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.
摘要翻译：纳米晶体非易失性存储器（NVM）在控制栅极和纳米晶体之间具有电介质，其具有足够的氮含量以减少电介质中的电子被俘获的位置。这是通过对氮浓度进行分级而实现的。靠近纳米晶体的氮浓度最高，其中电子/空穴阱的浓度趋于最高，并且朝向电子/空穴陷阱的浓度较低的对照栅极减小。已经发现这具有减少电荷被捕获的位置数量的有益效果。

98. 发明申请

US20080026526A1 METHOD FOR REMOVING NANOCLUSTERS FROM SELECTED REGIONS 有权
标题翻译：从选择地区移除纳米技术的方法
公开(公告)号：US20080026526A1
公开(公告)日：2008-01-31
申请号：US11459837
申请日：2006-07-25
申请人： Rajesh A. Rao , Tien Ying Luo , Ramachandran Muralidhar , Robert F. Steimle , Sherry G. Straub
发明人： Rajesh A. Rao , Tien Ying Luo , Ramachandran Muralidhar , Robert F. Steimle , Sherry G. Straub
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/28273 , H01L21/28282 , H01L21/32134 , H01L27/11526 , H01L27/11531 , H01L27/11573 , Y10S977/774 , Y10S977/779 , Y10S977/78 , Y10S977/943
摘要： A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.
摘要翻译：制造半导体器件的方法包括具有半导体层的衬底，该半导体层具有用于非易失性存储器的第一部分和不包括第一部分的第二部分。在半导体层上形成第一电介质层。在第一电介质层上进行等离子体氮化。在第一部分上形成第一多个纳米团簇，并在第二部分上形成第二多个纳米团簇。第二组纳米团簇被去除。在半导体层上方形成第二电介质层。在第二电介质层上形成导电层。

99. 发明授权

US07160775B2 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US07160775B2
公开(公告)日：2007-01-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
发明人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

100. 发明授权

US07105395B2 Programming and erasing structure for an NVM cell 有权
标题翻译： NVM单元的编程和擦除结构
公开(公告)号：US07105395B2
公开(公告)日：2006-09-12
申请号：US10930891
申请日：2004-08-31
申请人： James David Burnett , Gowrishankar L. Chindalore , Craig T. Swift , Ramachandran Muralidhar
发明人： James David Burnett , Gowrishankar L. Chindalore , Craig T. Swift , Ramachandran Muralidhar
IPC分类号： H01L29/72
CPC分类号： H01L29/0847 , H01L29/7881 , H01L29/7885
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.
摘要翻译：非易失性存储器（NVM）具有朝向衬底表面逐渐更加掺杂的硅锗（SiGe）漏极。衬底优选为硅，并且通过首先在漏极位置中的衬底中形成空腔来形成漏极。 SiGe在掺杂水平增加的情况下外延生长。因此，衬底和漏极之间的PN结在P和N侧都被轻掺杂。漏极逐渐变得更加重掺杂，直到达到最大期望的掺杂水平，并且SiGe漏极的剩余部分以该最大期望水平掺杂。作为进一步的增强，衬底中SiGe的周长与衬底和沟道的导电类型相同。因此，通道的一部分在SiGe中。

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