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91. 发明授权

US09287136B2 FinFET field-effect transistors with atomic layer doping 有权
标题翻译：具有原子层掺杂的FinFET场效应晶体管
公开(公告)号：US09287136B2
公开(公告)日：2016-03-15
申请号：US13606873
申请日：2012-09-07
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L29/78 , H01L27/088 , H01L21/20 , H01L21/24 , H01L21/314 , H01L21/02 , H01L29/36 , H01L21/225 , H01L29/66 , H01L29/165
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
摘要翻译：公开了使用原子层掺杂工艺制造的场效应晶体管。根据原子层掺杂方法的实施方案，制备半导体表面和掺杂剂气体混合物。此外，通过在小于500托的压力和300℃至750℃的温度下将掺杂剂气体混合物施加到半导体表面，在半导体表面上生长掺杂剂层。掺杂剂层包括在与半导体表面上的原子反应的每立方厘米的最小4×10 20有源掺杂剂原子使得反应的原子增加了半导体表面的导电性。

92. 发明授权

US08946680B2 TFET with nanowire source 有权
标题翻译：具有纳米线源的TFET
公开(公告)号：US08946680B2
公开(公告)日：2015-02-03
申请号：US13571657
申请日：2012-08-10
申请人： Sarunya Bangsaruntip , Isaac Lauer , Amlan Majumdar , Jeffrey Sleight
发明人： Sarunya Bangsaruntip , Isaac Lauer , Amlan Majumdar , Jeffrey Sleight
IPC分类号： H01L29/72 , H01L29/06 , B82Y10/00 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H01L29/739 , H01L29/78 , H01L29/40
CPC分类号： H01L29/0847 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0895 , H01L29/402 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66977 , H01L29/7391 , H01L29/775 , H01L29/78 , H01L29/78618 , H01L29/78696 , Y10S977/723 , Y10S977/938
摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
摘要翻译：隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。

93. 发明授权

US08318568B2 Tunnel field effect transistor 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US08318568B2
公开(公告)日：2012-11-27
申请号：US12760287
申请日：2010-04-14
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.
摘要翻译：公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。形成覆盖栅极堆叠和结的硬掩模。执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。去除硬掩模的注入部分，并露出其中一个接头。该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

94. 发明授权

US08258031B2 Fabrication of a vertical heterojunction tunnel-FET 有权
标题翻译：垂直异质结隧道FET的制造
公开(公告)号：US08258031B2
公开(公告)日：2012-09-04
申请号：US12815902
申请日：2010-06-15
申请人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
发明人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/165 , H01L29/7391
摘要： Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.
摘要翻译：示例性实施例包括用于制造异质结隧道场效应晶体管（FET）的方法，所述方法包括在绝缘体上硅（SOI）衬底的硅层上形成栅区，在硅层上形成漏极区邻近所述栅极区域并形成与所述栅极区域相邻的垂直异质结源区域，其中所述垂直异质结源区域产生与所述栅极区域相关联的栅极场列的隧道路径。

95. 发明申请

US20120193715A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 审中-公开
标题翻译：结构与纳米尺度尺寸上的等温硅吸收型材
公开(公告)号：US20120193715A1
公开(公告)日：2012-08-02
申请号：US13442008
申请日：2012-04-09
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接的氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

96. 发明申请

US20120193678A1 FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET 有权
标题翻译：垂直异步隧道式FET的制造
公开(公告)号：US20120193678A1
公开(公告)日：2012-08-02
申请号：US13430041
申请日：2012-03-26
申请人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
发明人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/165 , H01L29/7391
摘要： Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.
摘要翻译：示例性实施例包括用于制造异质结隧道场效应晶体管（FET）的方法，所述方法包括在绝缘体上硅（SOI）衬底的硅层上形成栅区，在硅层上形成漏极区邻近所述栅极区域并形成与所述栅极区域相邻的垂直异质结源区域，其中所述垂直异质结源区域产生与所述栅极区域相关联的栅极场列的隧道路径。

97. 发明申请

US20110278580A1 METHODOLOGY FOR FABRICATING ISOTROPICALLY SOURCE REGIONS OF CMOS TRANSISTORS 审中-公开
标题翻译：制造CMOS晶体管等电源区的方法
公开(公告)号：US20110278580A1
公开(公告)日：2011-11-17
申请号：US12779079
申请日：2010-05-13
申请人： Nicholas C. Fuller , Steve Koester , Isaac Lauer , Ying Zhang
发明人： Nicholas C. Fuller , Steve Koester , Isaac Lauer , Ying Zhang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/04 , H01L21/311
CPC分类号： H01L29/78675 , H01L21/3065 , H01L21/3083 , H01L21/84 , H01L29/66636 , H01L29/66659 , H01L29/7848 , H01L29/78618 , H01L29/78654
摘要： A method for fabricating recessed source regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.
摘要翻译：一种用于制造积极缩放CMOS器件的凹陷源区的方法。在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控制地在薄体的沟道中形成远远小于40nm的器件的源极的凹陷区域，以使SiGe，SiC的后续外延生长，或其他材料，并且随之而来的器件和环形振荡器性能的增加。还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

98. 发明申请

US20110278542A1 TFET with Nanowire Source 有权
标题翻译： TFET与纳米线源
公开(公告)号：US20110278542A1
公开(公告)日：2011-11-17
申请号：US12777881
申请日：2010-05-11
申请人： Sarunya Bangsaruntip , Isaac Lauer , Amlan Majumdar , Jeffrey Sleight
发明人： Sarunya Bangsaruntip , Isaac Lauer , Amlan Majumdar , Jeffrey Sleight
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/0847 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0895 , H01L29/402 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66977 , H01L29/7391 , H01L29/775 , H01L29/78 , H01L29/78618 , H01L29/78696 , Y10S977/723 , Y10S977/938
摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
摘要翻译：隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。

99. 发明申请

US20100038715A1 THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS 审中-公开
标题翻译：具有无边界自对准接触器的薄体硅绝缘体晶体管
公开(公告)号：US20100038715A1
公开(公告)日：2010-02-18
申请号：US12193392
申请日：2008-08-18
申请人： KATHERINA E. BABICH , Michael A. Guillorn , Isaac Lauer , Amlan Majumdar
发明人： KATHERINA E. BABICH , Michael A. Guillorn , Isaac Lauer , Amlan Majumdar
IPC分类号： H01L29/72 , H01L21/84
CPC分类号： H01L29/66628 , H01L29/6656 , H01L29/66772 , H01L29/78618
摘要： A method for fabricating a thin-silicon-on-insulator transistor with borderless self-aligned contacts is disclosed. A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode layer on the gate oxide layer. A hard mask on top of the gate stack is formed. An off-set spacer is formed surrounding the gate stack. A raised source/drain region is epitaxially formed adjacent to the off-set spacer. The raised source/drain region is grown slightly about a height of the gate stack including the hard mask. The raised source/drain region forms borderless self-aligned contact.
摘要翻译：公开了一种制造具有无边界自对准触点的绝缘体上硅晶体管的方法。栅极堆叠形成在掩埋氧化物层上方的硅层上。栅极堆叠包括在硅层上的栅极氧化物层和栅极氧化物层上的栅极电极层。形成了在栅极堆叠顶部的硬掩模。在栅堆叠周围形成偏置的间隔物。凸起的源极/漏极区域与偏置的间隔物相邻地外延形成。升高的源极/漏极区域围绕包括硬掩模的栅极堆叠的高度略微生长。升高的源极/漏极区域形成无边界自对准接触。

100. 发明授权

US09087772B2 Device and method for forming sharp extension region with controllable junction depth and lateral overlap 有权
公开(公告)号：US09087772B2
公开(公告)日：2015-07-21
申请号：US13611387
申请日：2012-09-12
申请人： Isaac Lauer , Effendi Leobandung , Ghavam G. Shahidi
发明人： Isaac Lauer , Effendi Leobandung , Ghavam G. Shahidi
IPC分类号： H01L29/76 , H01L21/265 , H01L21/306 , H01L21/3065 , H01L29/66 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L29/66492 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method for forming a semiconductor device includes forming a gate stack on a monocrystalline substrate. A surface of the substrate adjacent to the gate stack and below a portion of the gate stack is amorphorized. The surface is etched to selectively remove a thickness of amorphorized portions to form undercuts below the gate stack. A layer is epitaxially grown in the thickness and the undercuts to form an extension region for the semiconductor device. Devices are also provided.

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