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91. 发明申请

US20080048286A1 COPLANAR SILICON-ON-INSULATOR (SOI) REGIONS OF DIFFERENT CRYSTAL ORIENTATIONS AND METHODS OF MAKING THE SAME 有权
公开(公告)号：US20080048286A1
公开(公告)日：2008-02-28
申请号：US11929490
申请日：2007-10-30
申请人： Louis Hsu , Jack Mandelman
发明人： Louis Hsu , Jack Mandelman
IPC分类号： H01L29/00
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.

92. 发明申请

US20080048186A1 Design Structures Incorporating Semiconductor Device Structures with Self-Aligned Doped Regions 审中-公开
标题翻译：将半导体器件结构与自对准掺杂区域结合的设计结构
公开(公告)号：US20080048186A1
公开(公告)日：2008-02-28
申请号：US11876116
申请日：2007-10-22
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman
IPC分类号： H01L23/58
CPC分类号： H01L27/10841 , H01L27/10864 , H01L2924/0002 , H01L2924/00
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes semiconductor device structures with self-aligned doped regions. The semiconductor structure may include first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type.
摘要翻译：设计结构体现在用于设计，制造或测试其中设计结构包括具有自对准掺杂区域的半导体器件结构的设计的机器可读介质中。半导体结构可以包括限定在与沟槽的侧壁接合的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。半导体材料的中间区域分离第一和第二掺杂区域。第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。

93. 发明申请

US20070258213A1 Apparatuses for dissipating heat from semiconductor devices 有权
标题翻译：用于从半导体器件散热的装置
公开(公告)号：US20070258213A1
公开(公告)日：2007-11-08
申请号：US11416762
申请日：2006-05-03
申请人： Howard Chen , Hsichang Liu , Louis Hsu , Lawrence Mok
发明人： Howard Chen , Hsichang Liu , Louis Hsu , Lawrence Mok
IPC分类号： H05K7/20
CPC分类号： H01L23/427 , F28D15/0233 , F28D15/0275 , F28D15/04 , F28F2215/06 , H01L2224/16225
摘要： An apparatus for providing two-phase heat transfer for semiconductor devices includes a vapor chamber configured to carry a cooling liquid, the vapor chamber having base section, and a plurality of three-dimensional (3D) shaped members. The plurality of 3D-shaped members have interior and exterior sidewalls, the 3D-shaped members being connected to the base section so that vapor carrying latent heat can reach the respective interior sidewalls and get transferred to the respective exterior sidewalls configured to be in contact with an external coolant. The vapor chamber is configured to be in contact with a semiconductor device in order to remove heat therefrom.
摘要翻译：一种用于半导体器件的两相热传递装置，包括一个蒸气室，被配置为承载冷却液体，该蒸气室具有基部，以及多个三维（3D）形状的部件。多个3D形构件具有内部和外部侧壁，3D形构件连接到基部，使得携带潜热的蒸汽可以到达相应的内侧壁并被转移到被配置为与外部冷却液。蒸气室被配置为与半导体器件接触以从其中除去热量。

94. 发明申请

US20070252613A1 UNIVERSAL CMOS DEVICE LEAKAGE CHARACTERIZATION SYSTEM 有权
标题翻译：通用CMOS器件泄漏特性系统
公开(公告)号：US20070252613A1
公开(公告)日：2007-11-01
申请号：US11380515
申请日：2006-04-27
申请人： Louis Hsu , Edward Pillai , Joseph Natonio , James Rockrohr , David Hanson
发明人： Louis Hsu , Edward Pillai , Joseph Natonio , James Rockrohr , David Hanson
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/3008 , G01R31/318577
摘要： The invention provides a universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.
摘要翻译：本发明提供了一种通用泄漏监测系统（ULMS），用于在开发制造过程或正常操作期期间测量多个泄漏宏。 ULMS表征了栅极电介质泄漏，亚阈值泄漏和反向偏置结漏电以及n型和p型CMOS器件的泄漏等。使用片上算法从第一测试宏到最后一个测试宏顺序执行测试。当测试最后一个测试宏时，会扫描泄漏数据。

95. 发明申请

US20070187670A1 Opto-thermal annealing mask and method 失效
标题翻译：光热退火掩模和方法
公开(公告)号：US20070187670A1
公开(公告)日：2007-08-16
申请号：US11355799
申请日：2006-02-16
申请人： Louis Hsu , Jack Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
发明人： Louis Hsu , Jack Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
IPC分类号： H01L29/06
CPC分类号： H01L21/268 , H01L21/84 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.
摘要翻译：光热退火掩模层叠层包括位于衬底上的散热层。反射层位于热耗散层上。可以具有约10至约100埃厚度的透明覆盖层位于反射层上。光热退火掩模层可以用作场效应器件中的栅电极。

96. 发明申请

US20070111699A1 Method and apparatus for implementing enhanced hand shake protocol in microelectronic comunication systems 失效
标题翻译：在微电子通信系统中实现增强的手抖动协议的方法和装置
公开(公告)号：US20070111699A1
公开(公告)日：2007-05-17
申请号：US11282090
申请日：2005-11-17
申请人： Louis Hsu , Jack Mandelman , James Mason
发明人： Louis Hsu , Jack Mandelman , James Mason
IPC分类号： H04B1/16
CPC分类号： H04B1/38
摘要： A method and apparatus are provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the transmitter terminates communications, drops the common mode level with the idle input being activated.
摘要翻译：提供了一种用于实现用于微电子通信系统的增强的手抖动协议的方法和装置。发射机和接收机通过传输链路耦合在一起。发射机接收空闲输入。当发射机不发送数据并且发射机向接收单元应用第一共模电平时，空闲输入被激活。当发射机准备好传输数据并且发射机将共模电平提升到接收单元时，空闲输入被去激活。响应于接收机检测共模水平上移，接收器接收发送的数据信号。在所需数据被发送之后，发射机终止通信，在空闲输入被激活时降低共模电平。

97. 发明申请

US20070103350A1 Methods and apparatus for testing an integrated circuit 失效
标题翻译：用于测试集成电路的方法和装置
公开(公告)号：US20070103350A1
公开(公告)日：2007-05-10
申请号：US11272589
申请日：2005-11-10
申请人： Louis Hsu , Jack Mandelman , Joseph Marsh , Steven Zier
发明人： Louis Hsu , Jack Mandelman , Joseph Marsh , Steven Zier
IPC分类号： H03M1/10
CPC分类号： H03M1/1076
摘要： In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to test the analog circuit at a wafer level so as to detect a defect in one or more components of the analog circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供一种测试模拟电路的方法。该方法包括（1）向模拟电路提供一种适合于使模拟电路在测试期间像逻辑门一样起作用的屏蔽电路; 和（2）将数字信号施加到模拟电路以在晶片级测试模拟电路，以便检测模拟电路的一个或多个部件中的缺陷。提供了许多其他方面。

98. 发明申请

US20070103173A1 Systems and Methods for Controlling of Electro-Migration 有权
标题翻译：控制电迁移的系统和方法
公开(公告)号：US20070103173A1
公开(公告)日：2007-05-10
申请号：US11566796
申请日：2006-12-05
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R27/08
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译：公开了用于控制电迁移的系统和方法，并减少其有害影响。实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

99. 发明申请

US20070099326A1 eFuse and methods of manufacturing the same 有权
标题翻译： eFuse及其制造方法
公开(公告)号：US20070099326A1
公开(公告)日：2007-05-03
申请号：US11266740
申请日：2005-11-03
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是eFuse，包括（1）衬底的绝缘氧化物层上方的半导体层; （2）形成在半导体层中的二极管; 和（3）二极管上形成的硅化物层。提供了许多其他方面。

100. 发明申请

US20070057325A1 Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures 有权
标题翻译：具有封装的栅电极的半导体FinFET结构和用于形成这种半导体FinFET结构的方法
公开(公告)号：US20070057325A1
公开(公告)日：2007-03-15
申请号：US11225654
申请日：2005-09-13
申请人： Louis Hsu , Jack Mandelman
发明人： Louis Hsu , Jack Mandelman
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.
摘要翻译：其中FinFET的栅极被从引入掺杂剂的工艺掩模到FinFET的鳍状体中以形成源极/漏极区域的半导体结构以及制造这种半导体结构的方法。栅极掺杂以及因此栅电极的功函数有利地与掺杂鳍体以形成源极/漏极区的过程隔离。栅电极的侧壁由形成在栅电极上但不在鳍体的侧壁上的侧壁间隔物覆盖。

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