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91. 发明授权

US6113755A Apparatus for producing an electrode foil for use in aluminum electrolytic capacitors 失效
标题翻译：用于制造用于铝电解电容器的电极箔的装置
公开(公告)号：US6113755A
公开(公告)日：2000-09-05
申请号：US760722
申请日：1996-12-05
申请人： Masakazu Tanahashi , Kounosuke Hashio , Mitsuhisa Yoshimura , Daisuke Suzuki , Masanori Okabayashi , Shinji Kabeya
发明人： Masakazu Tanahashi , Kounosuke Hashio , Mitsuhisa Yoshimura , Daisuke Suzuki , Masanori Okabayashi , Shinji Kabeya
IPC分类号： H01G9/04 , C25D7/06 , C25D11/04 , C25D17/10 , H01G9/00 , H01G13/00
CPC分类号： H01G9/0029 , C25D11/04 , C25D17/10 , C25D7/0628 , C25D7/0642 , H01G13/00 , Y10S204/07
摘要： This invention provides an apparatus for producing an electrode foil for use in aluminum electrolytic capacitors with which a high capacitance is obtained while the distortion of the foil and the leakage current can be controlled. At least two electrode plates as cathode are disposed in an electrolytic tank containing an electrolytic solution, and a direct current is supplied between an aluminum foil as anode and the electrode plates. Anodization is conducted continuously by turning the direction of the aluminum foil via rollers and conveying the foil between the electrode plates. During this treatment, the length and the position of the effective sections of the electrode plates are adjusted to keep the length to be at most two-thirds of the distance between an area near the surface of the electrolytic solution and the upper part of the bottom roller, so that the peak value of the anodizing current density appears not at the surface of the electrolytic solution but in the electrolytic solution.
摘要翻译：本发明提供一种用于制造用于铝电解电容器的电极箔的设备，其中可以获得高电容，同时可以控制箔的变形和泄漏电流。将至少两个作为阴极的电极板设置在包含电解液的电解槽中，并且在作为阳极的铝箔和电极板之间提供直流电流。通过辊转动铝箔的方向并在电极板之间输送箔片来连续进行阳极氧化。在这种处理过程中，调节电极板的有效部分的长度和位置，使其长度保持在电解液表面附近与底部上部之间的距离的三分之二以上使得阳极氧化电流密度的峰值不出现在电解液的表面，而在电解液中。

92. 发明授权

US4949384A Driving apparatus 失效
标题翻译：驱动装置
公开(公告)号：US4949384A
公开(公告)日：1990-08-14
申请号：US414188
申请日：1989-09-28
申请人： Masao Noro , Daisuke Suzuki
发明人： Masao Noro , Daisuke Suzuki
IPC分类号： H04R3/04 , H04R1/28 , H04R3/00 , H04R3/12
CPC分类号： H04R1/2819 , H04R3/002
摘要： A driving apparatus for driving an electro-acoustic transducer comprises a power amplifier for supplying a drive power to the transducer, and a feedback circuit for generating a negative impedance. The feedback circuit has a main body portion connected to the amplifier and a control information storage body for storing control information for setting transmission characteristics of the feedback circuit. The storage body is arranged to be disconnected/connected to the main body portion. The main body portion comprises a plurality of transducer connection terminals connected to a plurality of transducers, respectively, a plurality of relays and normally-open contacts for selectively supplying an amplifier output to the transducer connection terminals. A transducer selection information is housed in the control information storage body. Thus, when the control information storage body is mounted in the main body portion in accordance with the transducer selection information, a relay and a contact is operated, the amplifier output is supplied to a predetermined transducer.
摘要翻译：用于驱动电声换能器的驱动装置包括用于向换能器提供驱动功率的功率放大器和用于产生负阻抗的反馈电路。反馈电路具有连接到放大器的主体部分和用于存储用于设置反馈电路的传输特性的控制信息的控制信息存储体。存储体被布置成与主体部分断开/连接。主体部分包括分别连接到多个换能器的多个换能器连接端子，多个继电器和常开触点，用于选择性地将放大器输出提供给换能器连接端子。换能器选择信息被容纳在控制信息存储体中。因此，当根据换能器选择信息将控制信息存储体安装在主体部分中时，继电器和触点被操作，放大器输出被提供给预定的换能器。

93. 发明授权

US11575161B2 Secondary battery protection circuit, secondary battery protection apparatus, battery pack and temperature detection circuit 有权
公开(公告)号：US11575161B2
公开(公告)日：2023-02-07
申请号：US17069121
申请日：2020-10-13
申请人： Yohei Watanabe , Takashi Takeda , Junji Takeshita , Daisuke Suzuki
发明人： Yohei Watanabe , Takashi Takeda , Junji Takeshita , Daisuke Suzuki
IPC分类号： H01M14/00 , H01M10/44 , H02J7/04 , H02J7/00 , H01M10/48
摘要： A secondary battery protection circuit for controlling charge and discharge using a switching circuit to protect a secondary battery from temperature is provided. The switching circuit is configured to be provided in a charge-and-discharge path between the secondary battery and an external device. The secondary battery protection circuit includes a detection terminal configured to be electrically connected, via a resistor, to between the switching circuit and the external device. The secondary battery protection circuit includes a first terminal configured to be electrically connected to a temperature detection terminal of the external device. The secondary battery protection circuit includes a second terminal to which a temperature sensitive element is configured to be electrically connected, the temperature sensitive element having a characteristic value varying in accordance with a change in temperature of the secondary battery.

94. 发明授权

US09349168B2 Image processing device and method to correct brightness signal of an input image 有权
标题翻译：用于校正输入图像的亮度信号的图像处理装置和方法
公开(公告)号：US09349168B2
公开(公告)日：2016-05-24
申请号：US14380629
申请日：2013-02-21
申请人： Tsubasa Onda , Yoshitaka Toyoda , Daisuke Suzuki , Koichi Yamashita , Narihiro Matoba
发明人： Tsubasa Onda , Yoshitaka Toyoda , Daisuke Suzuki , Koichi Yamashita , Narihiro Matoba
IPC分类号： G06K9/00 , G06K9/40 , G06T5/00 , H04N5/235 , H04N9/31 , H04N1/60 , H04N9/73 , H04N9/77
CPC分类号： G06T5/009 , G06T5/008 , G06T2207/10024 , G06T2207/20012 , H04N1/6027 , H04N5/235 , H04N5/2355 , H04N9/3179 , H04N9/73 , H04N9/77
摘要： A region determination circuit (60) determines whether or not each of the pixels in an image is within a region subject to correction, in which pixels having at most a predetermined brightness level appear with a frequency equal to or less than a predetermined value. An offset level generation circuit (10) generates an offset level (Offset) on the basis of the brightness of the pixels determined to be within the region subject to correction. An offset subtraction circuit (1) subtracts the offset level (Offset) from the image signal (Yi) to generate an offset image signal (Yofst). A gain generation circuit (20) generates a gain for the offset image signal (Yofst). A gain multiplication circuit (2) multiplies the offset image signal (Yofst) by the gain to generate a corrected image signal (Ya).
摘要翻译：区域确定电路（60）确定图像中的每个像素是否在经过校正的区域内，其中出现具有等于或小于预定值的频率的具有至多预定亮度级的像素。偏移电平生成电路（10）根据确定为在校正区域内的像素的亮度产生偏移电平（Offset）。偏移减法电路（1）从图像信号（Yi）中减去偏移电平（Offset），产生偏移图像信号（Yofst）。增益生成电路（20）产生偏移图像信号（Yofst）的增益。增益乘法电路（2）将偏移图像信号（Yofst）乘以增益以产生校正图像信号（Ya）。

95. 发明授权

US09116693B2 Arithmetic unit and arithmetic processing method for operating with higher and lower clock frequencies 有权
标题翻译：算术单元和算术处理方法，用于操作较高和较低的时钟频率
公开(公告)号：US09116693B2
公开(公告)日：2015-08-25
申请号：US13443507
申请日：2012-04-10
申请人： Daisuke Suzuki , Minoru Saeki , Yuichiro Nariyoshi
发明人： Daisuke Suzuki , Minoru Saeki , Yuichiro Nariyoshi
IPC分类号： G06F1/04 , G06F1/32
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/324 , G06F9/3001 , Y02D10/126
摘要： There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.
摘要翻译：需要提供能够根据接触使用或非接触使用来操作的无电池集成电路（IC）卡，防止协处理器吞吐量降低，尽管降低的时钟频率以减少非接触下的功耗使用，并确保非接触式使用下的高速处理。双接口卡是能够根据联系人使用或非接触使用来操作的无电池IC卡。双接口卡在接触式使用的高时钟下工作，在非接触式使用的情况下以低时钟工作。目标操作包括多个不同的基本操作。双接口卡包括基本运算电路组。在接触使用情况下，基本算术电路组在一个周期执行目标操作的一个基本操作。在非接触使用情况下，基本算术电路组在一个周期顺序地执行目标操作的至少两个基本操作。

96. 发明授权

US09106213B2 Bit generation apparatus and bit generation method 有权
标题翻译：位产生装置和位生成方法
公开(公告)号：US09106213B2
公开(公告)日：2015-08-11
申请号：US13978598
申请日：2011-01-13
申请人： Koichi Shimizu , Daisuke Suzuki , Tomomi Kasuya
发明人： Koichi Shimizu , Daisuke Suzuki , Tomomi Kasuya
IPC分类号： H03K9/08 , H03K3/02 , H03K5/1252 , H04L9/32 , H03K19/003
CPC分类号： H03K3/02 , G09C1/00 , H03K5/1252 , H03K19/003 , H03K19/00361 , H04L9/3278
摘要： A bit generation apparatus includes a glitch generation circuit that generates glitch signals which include a plurality of pulses, and T-FF bit generation circuits which input the glitch signals, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits generates a respective bit value based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits, circuits that are conventionally required but not essential for the glitch become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit.
摘要翻译：位产生装置包括产生包括多个脉冲的毛刺信号的毛刺产生电路和输入毛刺信号的T-FF位产生电路，并且基于包括在多个脉冲中的多个脉冲的上升沿或下降沿毛刺信号，产生0或1的位值.T-FF位产生电路中的每一个基于上升沿的奇偶性或多个下降沿的奇偶校验产生相应的位值的脉冲。作为使用T-FF位产生电路的结果，不需要通常需要但不是毛刺所必需的电路。这用于防止电路规模的扩展，并增加位产生电路的位产生的处理时间。

97. 发明申请

US20140089685A1 KEY INFORMATION GENERATION DEVICE AND KEY INFORMATION GENERATION METHOD 有权
标题翻译：关键信息生成装置和关键信息生成方法
公开(公告)号：US20140089685A1
公开(公告)日：2014-03-27
申请号：US14115251
申请日：2011-06-02
申请人： Daisuke Suzuki
发明人： Daisuke Suzuki
IPC分类号： H04L9/08
CPC分类号： H04L9/0866 , G06F12/14 , G06F21/50 , G06F21/70 , G06F2221/21 , G11B20/00086 , H04L9/3278
摘要： In initial generation (for example, shipping from the factory), a security device generates an identifier w specific to the security device, with the PUF technology, generates key information k (k=HF(k)) from the identifier w, generates encrypted confidential information x by encrypting (x=Enc(mk, k)) confidential information mk with the key information k, and stores the encrypted confidential information x and an authentication code h (h=HF′(k)) of the key information k, in a nonvolatile memory. In operation, the security device generates the identifier w with the PUF technology, generates the key information k from the identifier w, and decrypts the encrypted confidential information x with the key information k. At a timing where the identifier w is generated in the operation, the security device checks whether the current operating environment has largely changed from the initial generation (S311). If a change in operating environment is detected (S311→S312), the security device conducts a reset-up process (S312 to S315) of an authentication code h which is confidential information, and the encrypted confidential information x.
摘要翻译：在初始阶段（例如，出厂时），安全设备生成特定于安全设备的标识符w，利用PUF技术，从标识符w生成密钥信息k（k = HF（k）），生成加密机密信息x通过用密钥信息k加密（x = Enc（mk，k））机密信息mk，并且将加密的机密信息x和密钥信息k的认证码h（h = HF'（k））存储，在非易失性存储器中。在操作中，安全设备利用PUF技术生成标识符w，从标识符w生成密钥信息k，并用密钥信息k对加密的机密信息进行解密。在操作中生成标识符w的定时，安全装置检查当前的操作环境是否从初始生成发生了很大的变化（S311）。如果检测到操作环境发生变化（S311→S312），则安全装置进行作为机密信息的认证码h的复位处理（S312〜S315）和加密的机密信息x。

98. 发明授权

US08558516B2 Charge-controlling semiconductor integrated circuit and charging apparatus 有权
标题翻译：充电控制半导体集成电路和充电装置
公开(公告)号：US08558516B2
公开(公告)日：2013-10-15
申请号：US12467466
申请日：2009-05-18
申请人： Yoshihiro Takahashi , Daisuke Suzuki , Yoshihiro Motoichi , Gentaro Kurokawa
发明人： Yoshihiro Takahashi , Daisuke Suzuki , Yoshihiro Motoichi , Gentaro Kurokawa
IPC分类号： H02J7/06
CPC分类号： H02J7/00
摘要： A charge-controlling semiconductor integrated circuit includes a current- controlling MOS transistor which is connected between a voltage input terminal and an output terminal and controls flowing current, a substratum voltage switching circuit connected between the voltage input/output terminal and a substratum to which an input/output voltage is applied, and a voltage comparison circuit to compare the input/output voltage. The charge-controlling semiconductor integrated circuit controls the substratum voltage switching circuit based on an output of the voltage comparison circuit, and the voltage comparison circuit includes an intentional offset in a first potential direction. A level shift circuit to shift the output voltage to a potential direction opposite to the first potential direction is provided in a preceding stage of a first input terminal of the voltage comparison circuit, and the input voltage is input to a second input terminal of the voltage comparison circuit.
摘要翻译：电荷控制半导体集成电路包括电流控制MOS晶体管，其连接在电压输入端子和输出端子之间并控制流动电流;基极电压开关电路，连接在电压输入/输出端子与基板之间，施加输入/输出电压，以及比较输入/输出电压的电压比较电路。电荷控制半导体集成电路基于电压比较电路的输出控制基极电压开关电路，电压比较电路包括在第一电位方向上的有意偏移。在电压比较电路的第一输入端子的前级设置有将输出电压移位到与第一电位方向相反的电位方向的电平移位电路，输入电压输入到电压的第二输入端子比较电路。

99. 发明申请

US20130207597A1 CHARGE CIRCUIT 有权
标题翻译：充电电路
公开(公告)号：US20130207597A1
公开(公告)日：2013-08-15
申请号：US13756627
申请日：2013-02-01
申请人： Gentaro KUROKAWA , Daisuke Suzuki , Toshiki Sakamoto
发明人： Gentaro KUROKAWA , Daisuke Suzuki , Toshiki Sakamoto
IPC分类号： H02J7/00
CPC分类号： H02J7/0052 , H02J7/0029 , H02J7/007 , H02J7/0073 , H02J2007/0039 , H05B37/0281
摘要： A charge circuit includes a current limiting circuit configured to limit a current input from an input terminal; a first transistor connected between an output terminal of the current limiting circuit and a secondary battery; a charge control circuit configured to turn the first transistor on and off to start and stop supply of a charge current to the secondary battery; a second transistor configured to output a current proportional to the charge current flowing through the first transistor; and a charge timer configured to generate clock pulses according to the current output from the second transistor. The charge control circuit is configured to turn off the first transistor to stop the supply of the charge current to the secondary battery when the number of the clock pulses reaches a predetermined number.
摘要翻译：充电电路包括限流电路，其限制来自输入端的电流输入; 连接在限流电路的输出端子和二次电池之间的第一晶体管; 充电控制电路，被配置为使所述第一晶体管接通和断开，以开始和停止向所述二次电池供应充电电流; 第二晶体管，被配置为输出与流过所述第一晶体管的所述充电电流成比例的电流; 以及充电定时器，被配置为根据来自第二晶体管的电流输出产生时钟脉冲。充电控制电路被配置为当时钟脉冲的数量达到预定数量时，关闭第一晶体管以停止向二次电池的充电电流的供应。

100. 发明申请

US20130142741A1 METHOD FOR PRODUCING COMPOSITION FOR EXTERNAL USE CONTAINING PHYSIOLOGICALLY ACCEPTABLE SALT OF TRANEXAMATE 有权
标题翻译：用于生产含有生理学上可接受的盐酸盐的外用组合物的方法
公开(公告)号：US20130142741A1
公开(公告)日：2013-06-06
申请号：US13814549
申请日：2011-07-15
申请人： Masayoshi Miyamoto , Tomomi Kuromiya , Daisuke Suzuki
发明人： Masayoshi Miyamoto , Tomomi Kuromiya , Daisuke Suzuki
IPC分类号： A61K8/41 , A61K8/84 , A61K8/81 , A61Q19/02
CPC分类号： A61K8/8152 , A61K8/0295 , A61K8/41 , A61K8/73 , A61K8/84 , A61K2800/49 , A61K2800/805 , A61Q19/02
摘要： A composition for external use containing a tranexamate as an active ingredient with suppressed sticky or oily feeling but having a fresh feel of use, and a method for producing the same. A tranexamate salt can be dispersed stably in an aqueous medium by (a) dissolving the tranexamate salt and an amphiphilic polymer in water, a water-soluble organic solvent or a mixture thereof; and (b) adding a mixed solution obtained in the step (a) to an aqueous medium, and thus keeping the tranexamate salt in molecular assembly particles formed of the amphiphilic polymer.
摘要翻译：一种外用组合物及其制造方法，其中含有以氨基甲酸酯为活性成分的具有抑制的粘稠或油腻感，但具有清新的使用感的组合物。（a）将氨甲酯盐和两亲性聚合物溶于水，水溶性有机溶剂或其混合物中，稳定地分散在水性介质中; 和（b）将在步骤（a）中获得的混合溶液加入到水性介质中，从而将氨甲酯盐保持在由两亲性聚合物形成的分子组装颗粒中。

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